riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase

This commit is contained in:
tangxifan 2022-02-15 17:19:50 -08:00
parent ed6d557e65
commit e67f8ad8b2
4 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -363,6 +363,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string(BENCHMARK_PORT_POSTFIX),
std::string(FPGA_PORT_POSTFIX),
std::string(CHECKFLAG_PORT_POSTFIX),
std::string(),
std::string(ERROR_COUNTER),
atom_ctx,
netlist_annotation,

8
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -433,6 +433,7 @@ void print_verilog_testbench_check(std::fstream& fp,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& config_done_name,
const std::string& error_counter_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
@ -465,7 +466,12 @@ void print_verilog_testbench_check(std::fstream& fp,
fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl;
fp << "\t\t";
print_verilog_register_connection(fp, sim_start_port, sim_start_port, true);
fp << "\t\tend else begin" << std::endl;
fp << "\t\tend else " << std::endl;
/* If there is a config done signal specified, consider it as a trigger on checking */
if (!config_done_name.empty()) {
fp << "if (1'b1 == " << config_done_name << ") ";
}
fp << "begin" << std::endl;
for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) {
/* Bypass non-I/O atom blocks ! */

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -76,6 +76,7 @@ void print_verilog_testbench_check(std::fstream& fp,
const std::string& benchmark_port_postfix,
const std::string& fpga_port_postfix,
const std::string& check_flag_port_postfix,
const std::string& config_done_name,
const std::string& error_counter_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,

1
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2131,6 +2131,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX),
std::string(TOP_TB_CONFIG_DONE_PORT_NAME),
std::string(TOP_TESTBENCH_ERROR_COUNTER),
atom_ctx,
netlist_annotation,