Commit Graph

1114 Commits

Author SHA1 Message Date
tangxifan 592765af48 [core] code complete for upgrading netlist generator w.r.t. ccff v2 2023-04-23 13:57:37 +08:00
tangxifan 5500b9a289 [core] upgrading netlist generator 2023-04-22 16:27:27 +08:00
tangxifan ea8ae29b53 [core] code format 2023-04-22 15:12:38 +08:00
tangxifan 297a23dee7 [core] fixed syntax errors 2023-04-22 15:09:39 +08:00
tangxifan 5e8e982334 [core] finished developing checkers 2023-04-22 12:44:34 +08:00
tangxifan f70cc32824 [core] developing checkers for configuration protocol w.r.t. the programming clocks 2023-04-22 08:46:36 +08:00
tangxifan aeeee6d8bd [core] code format 2023-04-20 15:07:54 +08:00
tangxifan 40598d25a3 [core] fixed a bug which causes multi-clock programmable network failed in routing 2023-04-20 15:05:45 +08:00
tangxifan 928c7d5736 Merge branch 'master' into xt_clk_arch 2023-04-19 22:17:33 +08:00
tangxifan 9690cea115 [core] fix clang syntax 2023-04-19 15:46:42 +08:00
tangxifan cb4512b925 [core] code format 2023-04-19 11:10:42 +08:00
tangxifan a84cc52d7c [core] fixed a few bugs due to the changes in vtr regarding flat router 2023-04-19 11:08:18 +08:00
tangxifan 11f09db556 [core] fixed a bug where clock tracks do not pass through at higher level 2023-03-07 15:05:56 -08:00
tangxifan 50e201feeb [core] now clock routing for programmable clock network works for 1 clock design 2023-03-07 13:13:25 -08:00
tangxifan 550e68c68b [core] fixed a bug: node_fan_in seems buggy 2023-03-06 22:26:27 -08:00
tangxifan 2ff3ad61ce [core] format 2023-03-06 21:57:44 -08:00
tangxifan 45107bf14f [core] debugging 2023-03-06 21:48:19 -08:00
tangxifan c23b8e579d [core] fixed a bug 2023-03-06 17:10:14 -08:00
tangxifan 9823983b30 [core] debuggign 2023-03-06 15:57:37 -08:00
tangxifan 1633279c65 [core] fixed a bug in building edges for nodes 2023-03-06 14:50:28 -08:00
tangxifan 953625b1ca [core] format 2023-03-05 22:32:05 -08:00
tangxifan de1e300ec7 [core] now resize rr_node for clock graph is working 2023-03-05 22:21:55 -08:00
tangxifan 81e9187aac [core] debugging 2023-03-03 22:55:14 -08:00
tangxifan 4423d917fa [core] debugging 2023-03-03 18:00:43 -08:00
tangxifan 29ee6e7136 [core] debugging 2023-03-03 17:33:53 -08:00
tangxifan 5a43b451c1 [core] debugging 2023-03-03 16:56:20 -08:00
tangxifan c4ad21451c [core] debugging 2023-03-02 21:54:48 -08:00
tangxifan 46510388be [core] now fabric generator can wire clock ports to routing blocks 2023-03-02 12:33:26 -08:00
tangxifan 974263f0fa [core] dev 2023-03-01 23:27:29 -08:00
tangxifan 099d9f32f4 [core] dev 2023-03-01 16:08:15 -08:00
tangxifan 9baaf9ea06 [core] fix compiler warnings 2023-02-28 20:40:14 -08:00
tangxifan 7732907623 [core] format 2023-02-28 17:01:11 -08:00
tangxifan 2ff8fb8737 [core] wrapping up clock routing command 2023-02-28 16:52:54 -08:00
tangxifan bd2608d3e0 [core] dev 2023-02-28 15:41:37 -08:00
tangxifan 6f2572324e [core] developing route clock rr_graph command 2023-02-28 11:52:38 -08:00
tangxifan 8d5c21b14d [core] code format 2023-02-27 23:00:15 -08:00
tangxifan 2735b708d3 [core] reworked the tapping XML syntax 2023-02-27 22:59:44 -08:00
tangxifan ff69664c14 [core] syntax 2023-02-27 22:39:12 -08:00
tangxifan d4e19edc71 [core] finishing up clock rr_graph appending 2023-02-27 22:31:16 -08:00
tangxifan 2df1609616 [core] add a new API to get pin index from a tile 2023-02-27 21:44:00 -08:00
tangxifan 0dfe96bcf1 [core] dev 2023-02-27 19:37:49 -08:00
tangxifan b3dec93eb9 [core] code format 2023-02-27 15:12:59 -08:00
tangxifan 9ec4d690db [core] clock edges interconnecting clock tracks across levels 2023-02-27 15:10:36 -08:00
tangxifan b6eace8fac [core] now switch id is linked in clock network 2023-02-27 13:10:54 -08:00
tangxifan cae05a14e1 [core] dev 2023-02-26 23:10:50 -08:00
tangxifan 009d711ba5 [core] code format 2023-02-26 22:23:41 -08:00
tangxifan 87a9146082 [core] adding rr spatial lookup for clock nodes only 2023-02-26 22:23:17 -08:00
tangxifan db36f87dfa [core] enhance clock tree arch validation 2023-02-26 18:39:53 -08:00
tangxifan b9e5ae7ae9 [core] developing 2023-02-26 18:31:08 -08:00
tangxifan 780fc0f26d [core] developing validators and annotate rr_segment for clock arch 2023-02-26 18:03:55 -08:00
tangxifan 4bd952027f [core] dev 2023-02-26 15:31:07 -08:00
tangxifan 75773ddd4e [code] format 2023-02-26 12:46:29 -08:00
tangxifan 3db5acfb37 [core] dev 2023-02-26 12:40:13 -08:00
tangxifan 06f77d0435 [core] dev 2023-02-25 22:59:07 -08:00
tangxifan 8f0d94ba73 [code] format 2023-02-25 22:43:21 -08:00
tangxifan 0b33650761 [core] dev 2023-02-25 22:41:33 -08:00
tangxifan 8be6e7d0a0 [core] dev 2023-02-25 11:04:48 -08:00
tangxifan cf84e1df53 [core] dev 2023-02-24 22:50:27 -08:00
tangxifan 7f07a9d031 [lib] add default seg/switch to clock arch. Fixed syntax 2023-02-24 19:15:39 -08:00
tangxifan ee0459d729 [core] developing append_clock_rr_graph function 2023-02-24 17:58:37 -08:00
tangxifan aa55c692d7 [core] starting developing core function for clock rr_graph build-up 2023-02-23 18:04:07 -08:00
tangxifan 786b458a27 [core] adding new command 'append_clock_rr_graph' 2023-02-23 13:30:18 -08:00
tangxifan b78ca69fe5 [core] enable clock arch link 2023-02-22 22:29:16 -08:00
tangxifan e1dab3d227 [code] format 2023-02-22 22:01:24 -08:00
tangxifan e175472a07 [core] adding new commands 2023-02-22 21:58:25 -08:00
tangxifan f25dc461dc [code] format 2023-01-31 12:52:59 -08:00
tangxifan f00acf1e62 [code] fixed all the compiler warnings under openfpga/src 2023-01-31 12:51:52 -08:00
tangxifan 46368de6ff [script] now cmake allows strict compilation 2023-01-31 12:41:15 -08:00
tangxifan 101bb40d40 [engine] code format 2023-01-20 21:52:32 -08:00
tangxifan 059f8ca112 [engine] fixed a bug in repack when only invisible routing sinks are found 2023-01-20 21:50:59 -08:00
tangxifan 693404d1ac [engine] code format 2023-01-19 11:23:34 -08:00
tangxifan 3bcec24dca [engine] fixed a bug 2023-01-19 11:22:44 -08:00
tangxifan 2ba4249518 [engine] add black list for repacker to pick routing traces 2023-01-19 11:01:31 -08:00
tangxifan ac8c0e243c [core] code format 2023-01-15 12:13:59 -08:00
tangxifan cab7e04901 [core] fixed a bug in repacker to avoid routing constrained nets 2023-01-15 12:13:12 -08:00
tangxifan 2a0e512ac9 [code] format 2023-01-14 23:05:42 -08:00
tangxifan 4242c39b01 [core] fixed a bug in handling design constraints in repack 2023-01-14 23:05:04 -08:00
tangxifan c55d54d325 [code] format 2023-01-11 17:19:04 -08:00
tangxifan c00c43cbd4 [core] fixed a few bugs 2023-01-11 16:39:25 -08:00
tangxifan 9bbb09ef0f [core] adding a new command 'exec_external' to run system call 2023-01-11 16:31:26 -08:00
tangxifan b569d6b603 [core] format 2023-01-07 11:40:17 -08:00
tangxifan c7a4d25e35 [core] now all the commands can be optionally hidden 2023-01-07 11:36:10 -08:00
tangxifan 4385b364af [code] now setup command can be hidden optionally 2023-01-07 11:18:43 -08:00
tangxifan 9b5b1b0da7 [core] clang syntax error 2023-01-07 09:18:58 -08:00
tangxifan 52e803804d [core] add missing file 2023-01-06 22:37:55 -08:00
tangxifan 279e790fd8 [core] rename file to avoid collision 2023-01-06 21:41:52 -08:00
tangxifan 2fc047daff [core] format 2023-01-06 21:11:12 -08:00
tangxifan cf824e7161 [core] now bitstream commands follow templates 2023-01-06 21:08:50 -08:00
tangxifan 26c294679a [core] now setup commands follow templates 2023-01-06 20:52:37 -08:00
tangxifan a99794f51c [core] now FPGA-SDC commands follow templates 2023-01-06 19:22:51 -08:00
tangxifan 401b640852 [core] format 2023-01-06 17:50:47 -08:00
tangxifan 12134f4106 [core] now openfpga verilog commands follow templates 2023-01-06 17:48:00 -08:00
tangxifan 93c00207ab [core] now command functions are templates, which can be used by other extensions 2023-01-06 17:23:01 -08:00
tangxifan 5606566839 [engine] format 2023-01-01 17:37:44 -08:00
tangxifan 7610e536bf [engine] now 'source' command can be seen in help desk 2023-01-01 12:01:37 -08:00
tangxifan 76570e653c [engine] format 2023-01-01 10:23:18 -08:00
tangxifan c90f8389f1 [engine] debugged 2023-01-01 10:22:47 -08:00
tangxifan 8d947c7bdb [engine] now developers can write their superset command based on other commands through openfpga shell 2023-01-01 10:10:09 -08:00
tangxifan bffb4eedc9 [engine] typo 2022-12-30 18:18:51 -08:00
tangxifan d329f0bb44 [engine] code format 2022-12-30 18:17:19 -08:00