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[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``

This commit is contained in:
tangxifan 2022-02-01 12:17:02 -08:00
parent d8c1492a91
commit f311a034bb
6 changed files with 26 additions and 4 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -85,6 +85,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_use_relative_path = cmd.option("use_relative_path");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -98,6 +99,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_use_relative_path(cmd_context.option_enable(cmd, opt_use_relative_path));
options.set_print_top_testbench(true);
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -112,6 +112,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* Add an option '--use_relative_path' */
shell_cmd.add_option("use_relative_path", false, "Force to use relative path in netlists when including other netlists");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");

10
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -101,10 +101,10 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir_path,
const std::string& circuit_name,
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string verilog_fname = src_dir_path + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
@ -119,6 +119,12 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* If relative path is forced, we do not include an src_dir_path in the netlist */
std::string src_dir = src_dir_path;
if (options.use_relative_path()) {
src_dir.clear();
}
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {

2
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
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@ -23,7 +23,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const bool& use_relative_path,
const bool& include_time_stamp);
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
void print_verilog_full_testbench_include_netlists(const std::string& src_dir_path,
const std::string& circuit_name,
const VerilogTestbenchOption& options);

10
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
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@ -26,6 +26,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
time_unit_ = 1E-3;
time_stamp_ = true;
use_relative_path_ = false;
verbose_output_ = false;
}
@ -96,6 +97,10 @@ bool VerilogTestbenchOption::time_stamp() const {
return time_stamp_;
}
bool VerilogTestbenchOption::use_relative_path() const {
return use_relative_path_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -191,11 +196,14 @@ void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void VerilogTestbenchOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void VerilogTestbenchOption::set_use_relative_path(const bool& enabled) {
use_relative_path_ = enabled;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/verilog_testbench_options.h
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@ -48,6 +48,7 @@ class VerilogTestbenchOption {
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
bool time_stamp() const;
bool use_relative_path() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -75,6 +76,7 @@ class VerilogTestbenchOption {
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
void set_time_stamp(const bool& enabled);
void set_use_relative_path(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -92,6 +94,7 @@ class VerilogTestbenchOption {
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;
bool time_stamp_;
bool use_relative_path_;
bool verbose_output_;
};