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changing condition of bitstream downloading

This commit is contained in:
Emin Cetin 2022-01-27 11:49:55 +03:00
parent 7ed92b732f
commit 8f7ee4e338
1 changed files with 7 additions and 1 deletions
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8
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -1431,7 +1431,13 @@ void print_verilog_full_testbench_configuration_chain_bitstream(std::fstream& fp
fp << ";" << std::endl;
fp << "\t";
fp << "end else begin";
fp << "end else if (";
fp << TOP_TB_BITSTREAM_INDEX_REG_NAME;
fp << " >= 0 && ";
fp << TOP_TB_BITSTREAM_INDEX_REG_NAME;
fp << " < "
fp << "`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE;
fp << ") begin";
fp << std::endl;
fp << "\t\t";