[engine] avoid function naming conflicts
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510f453ea3
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800ce6a290
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@ -28,6 +28,7 @@ target_link_libraries(libopenfpga
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libpcf
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libvtrutil
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libbusgroup
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libpugixml
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libvpr)
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#Create the test executable
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@ -6,6 +6,7 @@
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "annotate_routing.h"
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#include "openfpga_annotate_routing.h"
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/* begin namespace openfpga */
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@ -16,38 +17,16 @@ namespace openfpga {
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* based on VPR routing results
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* - Unmapped rr_node will use invalid ids
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*******************************************************************/
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void annotate_rr_node_nets(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const RoutingContext& routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation,
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const bool& verbose) {
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size_t counter = 0;
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VTR_LOG("Annotating rr_node with routed nets...");
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VTR_LOGV(verbose, "\n");
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for (auto net_id : clustering_ctx.clb_nlist.nets()) {
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/* Ignore nets that are not routed */
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if (true == clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
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continue;
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}
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/* Ignore used in local cluster only, reserved one CLB pin */
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if (false == clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
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continue;
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}
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t_trace* tptr = routing_ctx.trace[net_id].head;
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while (tptr != nullptr) {
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RRNodeId rr_node = RRNodeId(tptr->index);
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/* Ignore source and sink nodes, they are the common node multiple starting and ending points */
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if ( (SOURCE != device_ctx.rr_graph.node_type(rr_node))
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&& (SINK != device_ctx.rr_graph.node_type(rr_node)) ) {
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vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
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counter++;
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}
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tptr = tptr->next;
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}
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void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const RoutingContext& routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation,
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const bool& verbose) {
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vtr::vector<RRNodeId, ClusterNetId> node2net = annotate_rr_node_nets(device_ctx, clustering_ctx, routing_ctx, verbose);
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for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes(); ++node_id) {
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vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id), node2net[RRNodeId(node_id)]);
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}
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VTR_LOG("Done with %d nodes mapping\n", counter);
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VTR_LOG("Loaded node-to-net mapping\n");
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}
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@ -15,11 +15,11 @@
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/* begin namespace openfpga */
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namespace openfpga {
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void annotate_rr_node_nets(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const RoutingContext& routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation,
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const bool& verbose);
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void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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const RoutingContext& routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation,
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const bool& verbose);
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void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx,
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const ClusteringContext& clustering_ctx,
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@ -112,9 +112,9 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
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*/
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openfpga_ctx.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
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annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
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openfpga_ctx.mutable_vpr_routing_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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annotate_vpr_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
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openfpga_ctx.mutable_vpr_routing_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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annotate_rr_node_previous_nodes(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
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openfpga_ctx.mutable_vpr_routing_annotation(),
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