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[engine] avoid function naming conflicts

This commit is contained in:
tangxifan 2022-08-18 19:33:56 -07:00
parent 510f453ea3
commit 800ce6a290
4 changed files with 19 additions and 39 deletions
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1
openfpga/CMakeLists.txt
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@ -28,6 +28,7 @@ target_link_libraries(libopenfpga
libpcf
libvtrutil
libbusgroup
libpugixml
libvpr)
#Create the test executable

41
openfpga/src/annotation/openfpga_annotate_routing.cpp
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@ -6,6 +6,7 @@
#include "vtr_assert.h"
#include "vtr_log.h"
#include "annotate_routing.h"
#include "openfpga_annotate_routing.h"
/* begin namespace openfpga */
@ -16,38 +17,16 @@ namespace openfpga {
* based on VPR routing results
* - Unmapped rr_node will use invalid ids
*******************************************************************/
void annotate_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
const RoutingContext& routing_ctx,
VprRoutingAnnotation& vpr_routing_annotation,
const bool& verbose) {
size_t counter = 0;
VTR_LOG("Annotating rr_node with routed nets...");
VTR_LOGV(verbose, "\n");
for (auto net_id : clustering_ctx.clb_nlist.nets()) {
/* Ignore nets that are not routed */
if (true == clustering_ctx.clb_nlist.net_is_ignored(net_id)) {
continue;
}
/* Ignore used in local cluster only, reserved one CLB pin */
if (false == clustering_ctx.clb_nlist.net_sinks(net_id).size()) {
continue;
}
t_trace* tptr = routing_ctx.trace[net_id].head;
while (tptr != nullptr) {
RRNodeId rr_node = RRNodeId(tptr->index);
/* Ignore source and sink nodes, they are the common node multiple starting and ending points */
if ( (SOURCE != device_ctx.rr_graph.node_type(rr_node))
&& (SINK != device_ctx.rr_graph.node_type(rr_node)) ) {
vpr_routing_annotation.set_rr_node_net(rr_node, net_id);
counter++;
}
tptr = tptr->next;
}
void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
const RoutingContext& routing_ctx,
VprRoutingAnnotation& vpr_routing_annotation,
const bool& verbose) {
vtr::vector<RRNodeId, ClusterNetId> node2net = annotate_rr_node_nets(device_ctx, clustering_ctx, routing_ctx, verbose);
for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes(); ++node_id) {
vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id), node2net[RRNodeId(node_id)]);
}
VTR_LOG("Done with %d nodes mapping\n", counter);
VTR_LOG("Loaded node-to-net mapping\n");
}

10
openfpga/src/annotation/openfpga_annotate_routing.h
View File

@ -15,11 +15,11 @@
/* begin namespace openfpga */
namespace openfpga {
void annotate_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
const RoutingContext& routing_ctx,
VprRoutingAnnotation& vpr_routing_annotation,
const bool& verbose);
void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
const RoutingContext& routing_ctx,
VprRoutingAnnotation& vpr_routing_annotation,
const bool& verbose);
void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,

6
openfpga/src/base/openfpga_link_arch.cpp
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@ -112,9 +112,9 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
*/
openfpga_ctx.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
openfpga_ctx.mutable_vpr_routing_annotation(),
cmd_context.option_enable(cmd, opt_verbose));
annotate_vpr_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
openfpga_ctx.mutable_vpr_routing_annotation(),
cmd_context.option_enable(cmd, opt_verbose));
annotate_rr_node_previous_nodes(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
openfpga_ctx.mutable_vpr_routing_annotation(),