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[Engine] Bug fix for missing WLR ports in auto-generated shift register banks

This commit is contained in:
tangxifan 2021-10-04 16:58:01 -07:00
parent fbef22b494
commit 3efd6840a8
1 changed files with 8 additions and 1 deletions
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9
openfpga/src/fabric/build_top_module_memory_bank.cpp
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@ -301,11 +301,18 @@ ModuleId build_wl_shift_register_chain_module(ModuleManager& module_manager,
circuit_lib.port_size(sram_output_ports[0]));
module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Add the output ports to output BL signals */
/* Add the output ports to output BL/WL signals */
BasicPort chain_wl_port(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME,
num_mems);
module_manager.add_port(mem_module, chain_wl_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Add the output ports to output WLR signals */
if (!sram_wlr_ports.empty()) {
BasicPort chain_wlr_port(WL_SHIFT_REGISTER_CHAIN_WLR_OUT_NAME,
num_mems);
module_manager.add_port(mem_module, chain_wlr_port, ModuleManager::MODULE_OUTPUT_PORT);
}
/* Find the sram module in the module manager */
ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));