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[engine] apply code format

This commit is contained in:
tangxifan 2022-10-06 18:13:33 -07:00
parent e2debd2dde
commit afdc071c4c
1 changed files with 4 additions and 5 deletions
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9
openfpga/src/fabric/module_manager.h
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@ -531,11 +531,10 @@ class ModuleManager {
vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_wire_; /* If the port is a wire, use for Verilog port definition. If
enabled: <port_type> reg <port_name> */
vtr::
vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_register_; /* If the port is a register, use for Verilog port
definition. If enabled: <port_type> reg <port_name>
*/
vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_register_; /* If the port is a register, use for Verilog port
definition. If enabled: <port_type> reg <port_name>
*/
vtr::vector<ModuleId, vtr::vector<ModulePortId, std::string>>
port_preproc_flags_; /* If a port is available only when a pre-processing
flag is enabled. This is to record the