From afdc071c4c76f2f8c560f2309e5ab5601b020ac1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 6 Oct 2022 18:13:33 -0700
Subject: [PATCH] [engine] apply code format

---
 openfpga/src/fabric/module_manager.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h
index 4c12873af..2c8633b42 100644
--- a/openfpga/src/fabric/module_manager.h
+++ b/openfpga/src/fabric/module_manager.h
@@ -531,11 +531,10 @@ class ModuleManager {
   vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
     port_is_wire_; /* If the port is a wire, use for Verilog port definition. If
                       enabled: <port_type> reg <port_name>  */
-  vtr::
-    vector<ModuleId, vtr::vector<ModulePortId, bool>>
-      port_is_register_; /* If the port is a register, use for Verilog port
-                            definition. If enabled: <port_type> reg <port_name>
-                          */
+  vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
+    port_is_register_; /* If the port is a register, use for Verilog port
+                          definition. If enabled: <port_type> reg <port_name>
+                        */
   vtr::vector<ModuleId, vtr::vector<ModulePortId, std::string>>
     port_preproc_flags_; /* If a port is available only when a pre-processing
                             flag is enabled. This is to record the