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[engine] adapting source files for new APIs in VTR

This commit is contained in:
tangxifan 2022-08-17 09:54:31 -07:00
parent d3d81f0b18
commit 716929536d
4 changed files with 27 additions and 11 deletions
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19
CMakeLists.txt
View File

@ -123,7 +123,24 @@ else ()
"-Wuninitialized" #Warn about unitialized values
"-Winit-self" #Warn about self-initialization
"-Wcatch-value=3" #Warn when catch statements don't catch by reference
"-Wextra-semi" #Warn about redudnant semicolons
"-Wextra-semi" #Warn about redudnant semicolons
"-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
#GCC-like optional
#"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods
#"-Wsuggest-final-methods" #Suggest where 'final' would help if specified on methods
#"-Wsuggest-override" #Suggest where 'override' should be specified
#"-Wold-style-cast" #Warn about using c-style casts
#"-Wconversion" #Warn when type conversions may change value
#"-Wsign-conversion" #Warn if a conversion may change the sign
#"-Wpadded" #Will warn if additional padding is introduced to a struct/class. Turn on if optimizing class memory layouts
#"-Wstrict-overflow=2" #Warn if the compiler optimizes assuming signed overflow does not occur
#"-Wfloat-equal" #Warn about using direct floating point equality
#"-Wunsafe-loop-optimizations" #Warn when loops can't be optimized
#"-Wswitch-enum" #Warn about uncovered enumeration values in a switch (even if there is a default)
#"-Wsign-promo" #Warn when overload resolution converts an unsigned type to signed when an unsigned overload exists
#"-Wdouble-promotion" #Warn when float is implicitly propted to double
#"-Wuseless-cast" #Warn about casts to the same type
#"-Wzero-as-null-pointer-constant" #Warn about using '0' instead of nullptr
)
endif()

2
openfpga/src/annotation/annotate_routing.cpp
View File

@ -154,7 +154,7 @@ void annotate_rr_node_previous_nodes(const DeviceContext& device_ctx,
t_trace* tptr = routing_ctx.trace[net_id].head;
while (tptr != nullptr) {
RRNodeId rr_node = tptr->index;
RRNodeId rr_node = RRNodeId(tptr->index);
/* Find the right previous node */
prev_node = find_previous_node_from_routing_traces(device_ctx.rr_graph,

15
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -11,7 +11,8 @@
#include "openfpga_side_manager.h"
/* Headers from vpr library */
#include "rr_graph_obj_utils.h"
#include "physical_types.h"
#include "rr_graph_view_util.h"
#include "openfpga_rr_graph_utils.h"
#include "annotate_rr_graph.h"
@ -19,8 +20,6 @@
/* begin namespace openfpga */
namespace openfpga {
constexpr char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__";
/* Build a RRChan Object with the given channel type and coorindators */
static
RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx,
@ -244,10 +243,10 @@ RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
rr_chan_dir.resize(rr_chan.get_chan_width());
for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
/* Identify the directionality, record it in rr_node_direction */
if (INC_DIRECTION == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack))) {
if (Direction::INC == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack))) {
rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0];
} else {
VTR_ASSERT(DEC_DIRECTION == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack)));
VTR_ASSERT(Direction::DEC == vpr_device_ctx.rr_graph.node_direction(rr_chan.get_node(itrack)));
rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1];
}
}
@ -492,8 +491,8 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx,
const bool& verbose_output) {
size_t count = 0;
for (size_t iswitch = 0; iswitch < vpr_device_ctx.rr_switch_inf.size(); ++iswitch) {
std::string switch_name(vpr_device_ctx.rr_switch_inf[iswitch].name);
for (const RRSwitchId& rr_switch_id : vpr_device_ctx.rr_graph.rr_switch()) {
std::string switch_name(vpr_device_ctx.rr_graph.rr_switch()[rr_switch_id].name);
/* Skip the delayless switch, which is only used by the edges between
* - SOURCE and OPIN
* - IPIN and SINK
@ -535,7 +534,7 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx,
}
/* Now update the device annotation */
vpr_device_annotation.add_rr_switch_circuit_model(RRSwitchId(iswitch), circuit_model);
vpr_device_annotation.add_rr_switch_circuit_model(rr_switch_id, circuit_model);
VTR_LOGV(verbose_output,
"Binded a routing resource graph switch '%s' to circuit model '%s'\n",
switch_name.c_str(),

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit f6844ecb7a70197553f33b5e3ad38a2ca79f9a98
Subproject commit 3653c773711ca7893e98372792b1b3e560bcf95e