[FPGA-Verilog] Fix bugs
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@ -40,14 +40,14 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
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if (use_relative_path) {
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src_dir.clear();
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}
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std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
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std::string verilog_fpath = src_dir_path + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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check_file_stream(verilog_fname.c_str(), fp);
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check_file_stream(verilog_fpath.c_str(), fp);
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/* Print the title */
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print_verilog_file_header(fp, std::string("Fabric Netlist Summary"), include_time_stamp);
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@ -212,7 +212,7 @@ void rec_print_verilog_logical_tile(NetlistManager& netlist_manager,
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fpath.c_str(), fp);
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@ -53,9 +53,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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check_file_stream(verilog_fpath.c_str(), fp);
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print_verilog_file_header(fp,
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std::string("Top-level Verilog module for FPGA"),
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