From 2b8e2de0c9c4043edde16645870ddbe4290570fc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 31 Jan 2022 14:23:04 -0800 Subject: [PATCH] [FPGA-Verilog] Fix bugs --- openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp | 6 +++--- openfpga/src/fpga_verilog/verilog_grid.cpp | 2 +- openfpga/src/fpga_verilog/verilog_top_module.cpp | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 76e8e1a36..fab23a825 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -40,14 +40,14 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, if (use_relative_path) { src_dir.clear(); } - std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME); + std::string verilog_fpath = src_dir_path + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME); /* Create the file stream */ std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc); /* Validate the file stream */ - check_file_stream(verilog_fname.c_str(), fp); + check_file_stream(verilog_fpath.c_str(), fp); /* Print the title */ print_verilog_file_header(fp, std::string("Fabric Netlist Summary"), include_time_stamp); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index fba75d145..8141029d2 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -212,7 +212,7 @@ void rec_print_verilog_logical_tile(NetlistManager& netlist_manager, /* Create the file stream */ std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc); check_file_stream(verilog_fpath.c_str(), fp); diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index f9d10b2bf..0d4084074 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -53,9 +53,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager, /* Create the file stream */ std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc); - check_file_stream(verilog_fname.c_str(), fp); + check_file_stream(verilog_fpath.c_str(), fp); print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA"),