tangxifan
|
2484150ab6
|
[core] working on port addition to top module
|
2023-06-23 12:21:47 -07:00 |
|
tangxifan
|
8bd9ae02fd
|
[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
|
tangxifan
|
7961223eac
|
[core] enabling io naming rules in fabric builder
|
2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
a4f26798b0
|
[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc
|
2023-06-19 11:59:48 -07:00 |
|
tangxifan
|
63ee0c980e
|
[core] fixed some bugs
|
2023-06-18 22:12:54 -07:00 |
|
tangxifan
|
d9499f2b40
|
[core] now fpga bitstream supports the wrapper module
|
2023-06-18 21:58:36 -07:00 |
|
tangxifan
|
c7ade72200
|
[core] code complete for the core wrapper creator. Start debugging
|
2023-06-18 19:17:42 -07:00 |
|
tangxifan
|
8bc70b590a
|
[core] developing fpga_core insertion
|
2023-06-17 23:42:45 -07:00 |
|
tangxifan
|
ee59bdb675
|
[core] code format
|
2023-06-07 18:55:34 -07:00 |
|
tangxifan
|
327f7f4dab
|
[core] now adapt to latest API of DeviceGrid
|
2023-06-07 18:54:48 -07:00 |
|
tangxifan
|
dab89322b3
|
[core] fixed the bug in I/O location map build-up when supporting subtiles
|
2023-05-04 09:51:05 +08:00 |
|
tangxifan
|
cb0e6b9e17
|
[core] fixed a critical bug
|
2023-05-03 21:46:35 +08:00 |
|
tangxifan
|
6c48c57421
|
[core] fixed some bugs in the subtile support
|
2023-05-03 21:23:52 +08:00 |
|
tangxifan
|
7bedc965ac
|
[core] supporting subtile
|
2023-05-03 17:30:58 +08:00 |
|
tangxifan
|
28b7a12f68
|
[core] code format
|
2023-04-23 14:31:35 +08:00 |
|
tangxifan
|
bd511ba515
|
[core] fixed syntax errors
|
2023-04-23 14:26:08 +08:00 |
|
tangxifan
|
592765af48
|
[core] code complete for upgrading netlist generator w.r.t. ccff v2
|
2023-04-23 13:57:37 +08:00 |
|
tangxifan
|
5500b9a289
|
[core] upgrading netlist generator
|
2023-04-22 16:27:27 +08:00 |
|
tangxifan
|
46510388be
|
[core] now fabric generator can wire clock ports to routing blocks
|
2023-03-02 12:33:26 -08:00 |
|
tangxifan
|
974263f0fa
|
[core] dev
|
2023-03-01 23:27:29 -08:00 |
|
tangxifan
|
099d9f32f4
|
[core] dev
|
2023-03-01 16:08:15 -08:00 |
|
tangxifan
|
afdc071c4c
|
[engine] apply code format
|
2022-10-06 18:13:33 -07:00 |
|
tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
|
2022-10-06 18:08:57 -07:00 |
|
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
|
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
|
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
|
tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
|
tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
|
tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
|
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
|
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
|
tangxifan
|
9e1abf5898
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 21:39:14 -07:00 |
|
tangxifan
|
d3f08a893c
|
[engine] now frame view will not build nets for configuration bus
|
2022-09-01 20:02:00 -07:00 |
|
tangxifan
|
0c2b49ddb9
|
[engine] remove debugging log output
|
2022-08-27 13:06:05 -07:00 |
|
tangxifan
|
b3e4a06969
|
[engine] adapt vpr wrapper to the latest main.cpp from vtr
|
2022-08-23 14:28:05 -07:00 |
|
tangxifan
|
892770a8fb
|
[engine] debugging subtile index failures
|
2022-08-23 14:13:10 -07:00 |
|
tangxifan
|
0a6b794ef0
|
[engine] fixed bugs in subtiles. Revisited the usage of client functions
|
2022-08-23 12:35:04 -07:00 |
|
tangxifan
|
019e663e12
|
[engine] fixing the bugs on building global nets to sub tile pins
|
2022-08-23 11:58:44 -07:00 |
|
tangxifan
|
e0ae851e28
|
[engine] correcting compilation errors due to vpr upgrade
|
2022-08-17 16:25:12 -07:00 |
|
tangxifan
|
ce32c3b30b
|
[engine] fixing api errors
|
2022-08-17 14:47:14 -07:00 |
|
tangxifan
|
3c2bf5159b
|
[engine] use new API to get node side
|
2022-08-17 14:38:40 -07:00 |
|
tangxifan
|
8f1aac885e
|
[engine] fixing mismatches in APIs
|
2022-08-17 14:19:02 -07:00 |
|
tangxifan
|
0c329866da
|
[engine] Use RRGraphView in openfpga source codes
|
2022-08-16 16:48:32 -07:00 |
|
tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
|
tangxifan
|
6586ea7816
|
[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
|
2021-10-11 09:40:02 -07:00 |
|
tangxifan
|
b9c540ec3f
|
[Engine] Upgrade fabric key writer to support BL/WL shift register banks
|
2021-10-10 21:14:14 -07:00 |
|
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
|
tangxifan
|
aac74d9163
|
[Engine] Bug fix
|
2021-10-09 18:46:20 -07:00 |
|
tangxifan
|
fa08f44107
|
[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
|
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
|
tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
|
2021-10-08 22:00:01 -07:00 |
|
tangxifan
|
e3ff40d9e0
|
[Engine] Add missing return value
|
2021-10-08 20:17:55 -07:00 |
|
tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
|
2021-10-08 17:58:06 -07:00 |
|
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
|
tangxifan
|
f7484d4323
|
[Engine] Update the key memory data structure to contain shift register bank general information
|
2021-10-08 10:42:18 -07:00 |
|
tangxifan
|
3efd6840a8
|
[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
|
2021-10-04 16:58:01 -07:00 |
|
tangxifan
|
28904ff526
|
[Engine] Bug fix on wrong port type for shift register chains
|
2021-10-03 12:31:58 -07:00 |
|
tangxifan
|
477c1cd062
|
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
|
2021-10-01 17:38:26 -07:00 |
|
tangxifan
|
977d81679d
|
[Engine] Upgrade check codes for WL CCFF
|
2021-10-01 17:23:10 -07:00 |
|
tangxifan
|
cf96d9ff01
|
[Engine] Add programming shift register clock to internal global port data structure
|
2021-10-01 11:05:31 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
|
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
|
2021-09-30 21:05:41 -07:00 |
|
tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
|
2021-09-29 20:34:25 -07:00 |
|
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
|
2021-09-29 20:21:46 -07:00 |
|
tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
|
2021-09-29 16:57:49 -07:00 |
|
tangxifan
|
ac6268d9ae
|
[Engine] Bug fix on compilation errors
|
2021-09-29 16:24:36 -07:00 |
|
tangxifan
|
c5ae93f177
|
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
|
2021-09-29 16:17:40 -07:00 |
|
tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
|
2021-09-28 23:27:47 -07:00 |
|
tangxifan
|
7723e00e6c
|
[Engine] Adding the function that builds a shift register module for BL/WLs
|
2021-09-28 22:49:24 -07:00 |
|
tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
|
2021-09-28 17:29:03 -07:00 |
|
tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |
|
tangxifan
|
ed80d6b3f4
|
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
|
tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
|
2021-09-05 12:01:38 -07:00 |
|
tangxifan
|
f75456e304
|
[Engine] Update BL/WL estimation function for QL memory bank protocol
|
2021-09-05 11:53:33 -07:00 |
|
tangxifan
|
5759f5f35b
|
[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
|
2021-09-03 17:55:23 -07:00 |
|
tangxifan
|
cbbf601edc
|
[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
|
tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
|
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
|
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
|
tangxifan
|
e6091fb3ff
|
[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
|
2021-02-18 21:56:30 -07:00 |
|
tangxifan
|
af4cc117fb
|
[Tool] bug fix in spypad lut
|
2021-02-09 22:53:18 -07:00 |
|
tangxifan
|
6a0f4f354f
|
[Tool] Support superLUT circuit model in core engine
|
2021-02-09 20:23:05 -07:00 |
|
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
|
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
|
2021-01-04 18:45:47 -07:00 |
|
tangxifan
|
804b721a19
|
[Tool] Bug fix in the configuration chain connection builder
|
2021-01-04 17:41:29 -07:00 |
|
tangxifan
|
bfd305b5a5
|
[Tool] Patch the bug in finding data output ports for CCFF
|
2021-01-04 17:22:30 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
cb2bd2e31c
|
[Tool] Remove register ports for mini local encoders (1-bit data out)
|
2020-12-06 14:21:54 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
3a708cff21
|
[Tool] Bug fix to enable nature fracturable LUT design
|
2020-11-25 23:01:18 -07:00 |
|
tangxifan
|
088198c861
|
[Tool] enhance error checking in fabric key parser
|
2020-11-13 10:56:00 -07:00 |
|
tangxifan
|
372fb261fd
|
[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
|
tangxifan
|
9cbc374b33
|
[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
cbb1545ee3
|
[Tool] Add connection builder for tile global ports to top-level module
|
2020-11-10 16:59:00 -07:00 |
|
tangxifan
|
9b0617ffe6
|
[Tool] Bug fix for mappable I/O support
|
2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
4a2874b2bc
|
[Tool] Refactor the codes for walking through io blocks
|
2020-11-03 13:21:50 -07:00 |
|
tangxifan
|
e4d974c5c8
|
[Tool] Split io location mapping builder from fabric builder
|
2020-11-02 18:27:34 -07:00 |
|
tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
|
2020-10-30 17:29:04 -06:00 |
|
tangxifan
|
0d77916041
|
[Tool] Support multi-region frame-based configuration protocol
|
2020-10-30 10:43:11 -06:00 |
|
tangxifan
|
8ef6ae32fb
|
[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
|
2020-10-29 17:35:55 -06:00 |
|
tangxifan
|
987eccf586
|
[Tool] Bug fix in multi-region memory bank; Basic test passed
|
2020-10-29 16:26:45 -06:00 |
|
tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
|
2020-10-29 12:42:03 -06:00 |
|
tangxifan
|
bd49ea95d4
|
[Tool] Add function to comput configuration bits by region
|
2020-10-28 12:37:09 -06:00 |
|
tangxifan
|
446f982410
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[Tool] Add warning when number of regions defined in fabric key is different than architecture
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2020-10-28 11:43:05 -06:00 |
|
tangxifan
|
e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
|
tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 14:54:51 -06:00 |
|
tangxifan
|
9adeb550dc
|
[OpenFPGA Tool] Bug fix in fabric builder
|
2020-09-23 18:28:00 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
66e5e141a1
|
improve fabric key loader to reduce runtime
|
2020-07-07 10:19:34 -06:00 |
|
tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
|
tangxifan
|
83e26adf90
|
add module usage types for future FPGA-SPICE development
|
2020-07-04 22:33:54 -06:00 |
|
tangxifan
|
adee87569d
|
enable fast bitstream building by creating a frame view of fabric
|
2020-07-02 16:25:36 -06:00 |
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tangxifan
|
81ecfa3197
|
add comments to clarify how to select CB ports when connecting to SBs at the top level
|
2020-07-01 14:44:40 -06:00 |
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tangxifan
|
0a3c746fb1
|
now split CB module bus ports into lower/upper parts
|
2020-07-01 14:37:13 -06:00 |
|
tangxifan
|
1015880d0e
|
use easy-to-access net look up in switch block module builder
|
2020-06-30 18:15:41 -06:00 |
|
tangxifan
|
05187f8aa4
|
use typedef to short the module pin information
|
2020-06-30 18:07:22 -06:00 |
|
tangxifan
|
2e7684b746
|
adapt bus ports in connection block module builder
|
2020-06-30 17:50:53 -06:00 |
|
tangxifan
|
2ef083c49d
|
adapt SB module builder to use bus ports
|
2020-06-30 16:02:40 -06:00 |
|
tangxifan
|
f023652ac4
|
keep optimizing memory footprint of module manager by using net terminal storage
|
2020-06-30 14:18:05 -06:00 |
|
tangxifan
|
f49cabeeda
|
optimize memory efficiency for module net id storage
|
2020-06-30 11:33:06 -06:00 |
|
tangxifan
|
23bcad0678
|
use more robust net builder in inter tile connections
|
2020-06-30 10:49:17 -06:00 |
|
tangxifan
|
025d4a3599
|
use efficient net builder in top module connection builder
|
2020-06-29 23:28:26 -06:00 |
|
tangxifan
|
e7d5736269
|
add profile time to top module builder for better spot on runtime/memory overhead sources
|
2020-06-29 23:17:03 -06:00 |
|
tangxifan
|
57e6c84252
|
add reserve net sources and sinks to module manager
|
2020-06-29 22:49:11 -06:00 |
|
tangxifan
|
66746f69da
|
optimizing memory efficiency by reserving nets in module manager
|
2020-06-29 21:27:43 -06:00 |
|
tangxifan
|
9d32a5b81f
|
add alias name support for fabric key
|
2020-06-27 14:59:53 -06:00 |
|
tangxifan
|
a5055e9d26
|
add support about loading external fabric key
|
2020-06-12 13:03:11 -06:00 |
|
tangxifan
|
9dbf536306
|
add shuffled configurable children support for top module
|
2020-06-12 11:16:53 -06:00 |
|
tangxifan
|
cf9c3b0f44
|
add write fabric to test cases
|
2020-06-12 10:50:23 -06:00 |
|
tangxifan
|
3499b4d3e7
|
add fabric key writer for top-level module
|
2020-06-12 10:41:34 -06:00 |
|
tangxifan
|
8a4ec85c39
|
add configurable children-related methods to module manager
|
2020-06-11 21:44:25 -06:00 |
|
tangxifan
|
3c10af7f2b
|
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
0e16ee1030
|
add configuration bus nets for memory bank decoders at top module
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
fa8dfc1fbd
|
add configuration protocol ports to top module for memory bank organization
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
8ec8ac4118
|
bug fixed in flatten memory organization. Passed verification
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b9aac3cbdf
|
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
d2d443a988
|
start developing memory bank and standalone configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
c696e3d20f
|
refine frame-based memory addition to compact the area
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
ed2325ec9e
|
add frame decoder build-up to top-level module
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
10e1a4b2fe
|
format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
5a8c05378e
|
add --depth option to fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
56e0d2a918
|
critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
|
2020-04-13 12:58:44 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
92a3a444f9
|
update VPR7 to support global I/O ports
|
2020-04-06 20:44:00 -06:00 |
|
tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
|
2020-04-05 17:26:44 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
836f722f20
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
tangxifan
|
63306ce3a0
|
add comments to explain the memory organization in the top-level module
|
2020-04-01 11:05:30 -06:00 |
|
tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
|
tangxifan
|
7b9384f3b2
|
add write_gsb command to shell interface
|
2020-03-21 19:40:26 -06:00 |
|
tangxifan
|
c0e8d98c6f
|
bug fixed in tile direct builder
|
2020-03-21 12:43:56 -06:00 |
|
tangxifan
|
05ec86430a
|
temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
|
2020-03-20 17:56:03 -06:00 |
|
tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |