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[core] fixed some bugs in the subtile support

This commit is contained in:
tangxifan 2023-05-03 21:23:52 +08:00
parent 7bedc965ac
commit 6c48c57421
5 changed files with 81 additions and 77 deletions
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83
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
View File

@ -151,6 +151,7 @@ void add_grid_module_duplicated_pb_type_ports(
static void add_grid_module_net_connect_duplicated_pb_graph_pin(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
@ -169,15 +170,18 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
}
/* num_pins/capacity = the number of pins that each type_descriptor has.
* Capacity defines the number of type_descriptors in each grid
* so the pin index at grid level = pin_index_in_type_descriptor
* + type_descriptor_index_in_capacity *
* num_pins_per_type_descriptor
/* Note that each grid may contain a number of sub tiles, each type of which
* may a different capacity and number of pins We need to find the start pin
* index for a given z offset (instance id), denotes the index of the first
* pin regarding the current instance. The variable 'pin_count_in_cluster'
* represent the pin index in the context of current instance only. With the
* information above, we can then calculate the absolute pin index at
* grid-level (considering all the sub tiles).
*/
size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster +
child_instance * grid_type_descriptor->num_pins /
grid_type_descriptor->capacity;
size_t grid_pin_index =
pb_graph_pin->pin_count_in_cluster +
vpr_device_annotation.physical_tile_z_to_start_pin_index(
grid_type_descriptor, child_inst_subtile_index);
int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index];
int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
@ -292,49 +296,48 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
void add_grid_module_nets_connect_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
/* FIXME: Currently support only 1 equivalent site! Should clarify this
* limitation in documentation! */
for (const t_sub_tile& sub_tile : grid_type_descriptor->sub_tiles) {
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);
size_t child_inst_subtile_index = sub_tile.capacity.low + child_instance;
for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
}
for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport];
++ipin) {
add_grid_module_net_connect_duplicated_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport];
++ipin) {
add_grid_module_net_connect_duplicated_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
}
}
for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
}
}

2
openfpga/src/fabric/build_grid_module_duplicated_pins.h
View File

@ -24,7 +24,7 @@ void add_grid_module_duplicated_pb_type_ports(
void add_grid_module_nets_connect_duplicated_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side);
} /* end namespace openfpga */

3
openfpga/src/fabric/build_grid_module_utils.cpp
View File

@ -43,6 +43,7 @@ std::vector<e_side> find_grid_module_pin_sides(
void add_grid_module_net_connect_pb_graph_pin(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
@ -69,7 +70,7 @@ void add_grid_module_net_connect_pb_graph_pin(
size_t grid_pin_index =
pb_graph_pin->pin_count_in_cluster +
vpr_device_annotation.physical_tile_z_to_start_pin_index(
grid_type_descriptor, child_instance);
grid_type_descriptor, child_inst_subtile_index);
int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index];
for (const e_side& side : grid_pin_sides) {

1
openfpga/src/fabric/build_grid_module_utils.h
View File

@ -23,6 +23,7 @@ std::vector<e_side> find_grid_module_pin_sides(
void add_grid_module_net_connect_pb_graph_pin(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const size_t& child_inst_subtile_index,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,

69
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -108,50 +108,49 @@ static void add_grid_module_pb_type_ports(
static void add_grid_module_nets_connect_pb_type_ports(
ModuleManager& module_manager, const ModuleId& grid_module,
const ModuleId& child_module, const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
/* FIXME: Currently support only 1 equivalent site! Should clarify this
* limitation in documentation! */
for (const t_sub_tile& sub_tile : grid_type_descriptor->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);
size_t child_inst_subtile_index = sub_tile.capacity.low + child_instance;
for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
}
for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
OUTPUT2OUTPUT_INTERC);
}
}
for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport];
++ipin) {
add_grid_module_net_connect_pb_graph_pin(
module_manager, grid_module, child_module, child_instance,
child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]), border_side,
INPUT2INPUT_INTERC);
}
}
}
@ -1154,7 +1153,7 @@ static void build_physical_tile_module(
for (const size_t& child_instance :
module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_pb_type_ports(
module_manager, grid_module, pb_module, child_instance,
module_manager, grid_module, pb_module, child_instance, sub_tile,
vpr_device_annotation, phy_block_type, border_side);
}
}
@ -1180,7 +1179,7 @@ static void build_physical_tile_module(
for (const size_t& child_instance :
module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_duplicated_pb_type_ports(
module_manager, grid_module, pb_module, child_instance,
module_manager, grid_module, pb_module, child_instance, sub_tile,
vpr_device_annotation, phy_block_type, border_side);
}
}