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[core] supporting subtile

This commit is contained in:
tangxifan 2023-05-03 17:30:58 +08:00
parent df771cb33a
commit 7bedc965ac
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fabric/build_grid_modules.cpp
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@ -1094,7 +1094,7 @@ static void build_physical_tile_module(
* it as a mode under a <pb_type>
*/
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
for (int iz = 0; iz < sub_tile.capacity.total(); ++iz) {
for (int iz = sub_tile.capacity.low; iz < sub_tile.capacity.high; ++iz) {
VTR_ASSERT(1 == sub_tile.equivalent_sites.size());
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
/* Bypass empty pb_graph */