From 7bedc965ac814361ecd915874faa10078a2c6dc9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 3 May 2023 17:30:58 +0800
Subject: [PATCH] [core] supporting subtile

---
 openfpga/src/fabric/build_grid_modules.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp
index 6773273f7..10fbd6704 100644
--- a/openfpga/src/fabric/build_grid_modules.cpp
+++ b/openfpga/src/fabric/build_grid_modules.cpp
@@ -1094,7 +1094,7 @@ static void build_physical_tile_module(
    * it as a mode under a <pb_type>
    */
   for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
-    for (int iz = 0; iz < sub_tile.capacity.total(); ++iz) {
+    for (int iz = sub_tile.capacity.low; iz < sub_tile.capacity.high; ++iz) {
       VTR_ASSERT(1 == sub_tile.equivalent_sites.size());
       t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
       /* Bypass empty pb_graph */