Commit Graph

376 Commits

Author SHA1 Message Date
tangxifan 52ae484a7c [core] fixed a bug on messed up wire connections for OPINs 2024-05-20 13:50:31 -07:00
tangxifan b554a3d855 [core] code format 2024-05-19 17:24:38 -07:00
tangxifan 56aaa6a1f4 [core] sytax 2024-05-19 17:23:48 -07:00
tangxifan 065d77c679 [core] supporting opin connection to cb in tiles 2024-05-19 17:04:24 -07:00
tangxifan 9079056871 [core] now connect OPIN to CB in top-level module 2024-05-19 14:27:36 -07:00
tangxifan 918bf79ca3 [core] update vtr and developing caches for OPIN lists just for connection blocks 2024-05-19 14:10:00 -07:00
tangxifan 772da3006b [core] code format 2024-05-18 22:19:17 -07:00
tangxifan 304f34525e [core] syntax 2024-05-18 22:17:52 -07:00
tangxifan b533ea4060 [core] now cb module include OPIN nodes 2024-05-18 22:00:02 -07:00
tangxifan 3d8107487c [core] code format 2024-05-03 10:21:39 -07:00
tangxifan c7501cb9b7 [core] fixed the bugs when there are module renaming 2024-05-03 10:20:19 -07:00
tangxifan f41a5e8b89 [core] fixed some bugs 2024-05-02 22:49:06 -07:00
tangxifan c557b0104a [core] avoid unwanted tab 2024-05-02 21:34:12 -07:00
tangxifan b85ec28eb8 [core] code format 2024-05-02 21:17:17 -07:00
tangxifan d3b1e562ad [core] fixed some bugs on format 2024-05-02 21:11:20 -07:00
tangxifan bf24382f19 [core] code format 2024-05-02 18:33:07 -07:00
tangxifan a2fb84dfa9 [core] add fabric hierarchy writer 2024-05-02 18:30:20 -07:00
tangxifan 4d3447f773 [core] rework fabric hierarchy writer 2024-05-02 18:05:38 -07:00
chungshien dd577e37e0
LUTRAM Support (#1595)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric

* LUTRAM Support Phase 1

* Add Test

* Add more protocol checking to enable LUTRAM feature

* Move the config setting under config protocol

* Revert any changes

---------

Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
tangxifan 08bd6d00d3 [core] code format 2024-04-11 15:04:08 -07:00
tangxifan 79970719b4 [core] fixed a bug where regex breaks 2024-04-11 14:59:14 -07:00
tangxifan f63ea06c4e [core] now support regular expression in module name for fabric pin physical location output 2024-04-11 14:30:27 -07:00
tangxifan 5960cc14aa [core] fixed a bug 2024-04-11 13:04:47 -07:00
tangxifan 6f94399767 [core] code format 2024-04-10 22:53:52 -07:00
tangxifan 971f0e8838 [core] add a new option '--show_invalid_side' 2024-04-10 22:52:36 -07:00
tangxifan 58708ff727 [core] syntax 2024-04-10 20:08:02 -07:00
tangxifan 435e83c530 [core] add port side to tile ports 2024-04-10 17:38:02 -07:00
tangxifan f9f7d42d93 [core] add port side attribute and set them when buidling grid/cb/sb modules 2024-04-10 17:10:06 -07:00
tangxifan d156de060e [core] adding pin side attribute to module manager 2024-04-10 16:19:28 -07:00
tangxifan b0be9fe75d [core] developing xml writer for fabric pin phy loc 2024-04-10 15:51:26 -07:00
tangxifan 47baaff94c [core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func 2024-04-10 13:30:02 -07:00
tangxifan 3d4f1505b6 [core] code format 2023-10-20 22:02:56 -07:00
tangxifan 66c3226fad [core] now follow module unique index when naming grouped configuration memories 2023-10-20 22:01:19 -07:00
tangxifan e4b204f2e4 [core] code format 2023-10-20 21:14:07 -07:00
tangxifan 76a4b8a82b [core] remove the prefix of grouped memory blocks 2023-10-20 21:13:37 -07:00
tangxifan c4bce834e4 [core] code format 2023-09-25 22:34:39 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 1624dc9764 [core] code format 2023-09-25 21:13:50 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00
tangxifan dbd466cdec [core] now support tile port merge 2023-09-25 18:16:24 -07:00
tangxifan 3adf81046a [core] code format 2023-09-25 17:22:26 -07:00
tangxifan 5e269e8bc4 [core] support port merging at grid modules 2023-09-25 17:21:58 -07:00
tangxifan edb0e687f1 [core] code format 2023-09-23 12:15:53 -07:00
tangxifan 11de8965a8 [core] fixed some bugs 2023-09-23 12:15:31 -07:00
tangxifan 860cfd53c6 [core] fixed critical bugs in renaming modules 2023-09-23 11:51:31 -07:00
tangxifan ca3617a029 [core] code format 2023-09-20 20:37:27 -07:00
tangxifan 1ef38b6a64 [core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming 2023-09-20 20:34:21 -07:00
tangxifan c105b56bf0 [core] code format 2023-09-18 23:31:27 -07:00
tangxifan 43fd08a3fe [core] fixed a bug 2023-09-18 23:31:09 -07:00
tangxifan 1daabb990e [core] code format 2023-09-18 15:35:13 -07:00