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[core] now cb module include OPIN nodes

This commit is contained in:
tangxifan 2024-05-18 22:00:02 -07:00
parent 926b9e9739
commit b533ea4060
3 changed files with 96 additions and 3 deletions
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42
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -320,6 +320,39 @@ ModulePortId find_connection_block_module_ipin_port(
return ipin_port_id;
}
/*********************************************************************
* Generate a port for a connection block
********************************************************************/
ModulePortId find_connection_block_module_opin_port(
const ModuleManager& module_manager, const ModuleId& cb_module,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const RRGraphView& rr_graph, const RRGSB& rr_gsb,
const RRNodeId& src_rr_node) {
/* Ensure the src_rr_node is an input pin of a CLB */
VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node));
/* Create port description for input pin of a CLB */
vtr::Point<size_t> port_coord(rr_graph.node_xlow(src_rr_node),
rr_graph.node_ylow(src_rr_node));
/* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB
*/
enum e_side cb_opin_side = NUM_SIDES;
int cb_opin_index = -1;
rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side,
cb_opin_index);
/* We need to be sure that drive_rr_node is part of the CB */
VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side));
std::string port_name = generate_cb_module_grid_port_name(
cb_opin_side, grids, vpr_device_annotation, rr_graph,
rr_gsb.get_opin_node(cb_opin_side, cb_opin_index));
/* Must find a valid port id in the Switch Block module */
ModulePortId opin_port_id =
module_manager.find_module_port(cb_module, port_name);
VTR_ASSERT(true ==
module_manager.valid_module_port_id(cb_module, opin_port_id));
return opin_port_id;
}
/*********************************************************************
* Generate a list of routing track middle output ports
* for routing multiplexer inside the connection block
@ -331,8 +364,13 @@ std::vector<ModulePinInfo> find_connection_block_module_input_ports(
std::vector<ModulePinInfo> input_ports;
for (auto input_rr_node : input_rr_nodes) {
input_ports.push_back(find_connection_block_module_chan_port(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));
if (OPIN == rr_graph.node_type(input_rr_node)) {
input_ports.push_back(find_connection_block_module_opin_port(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));
} else {
input_ports.push_back(find_connection_block_module_chan_port(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));
}
}
return input_ports;

6
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -62,6 +62,12 @@ ModulePortId find_connection_block_module_ipin_port(
const RRGraphView& rr_graph, const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);
ModulePortId find_connection_block_module_opin_port(
const ModuleManager& module_manager, const ModuleId& cb_module,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const RRGraphView& rr_graph, const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);
std::vector<ModulePinInfo> find_connection_block_module_input_ports(
const ModuleManager& module_manager, const ModuleId& cb_module,
const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type,

51
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -978,7 +978,7 @@ static void build_connection_block_module(
enum e_side cb_ipin_side = cb_ipin_sides[iside];
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side);
++inode) {
const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
vtr::Point<size_t> port_coord(rr_graph.node_xlow(ipin_node),
rr_graph.node_ylow(ipin_node));
std::string port_name = generate_cb_module_grid_port_name(
@ -993,6 +993,44 @@ static void build_connection_block_module(
}
}
/* Add the output pins of grids which are input ports of the connection block, if there is any */
std::vector<RRNodeId> opin_rr_nodes;
for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
enum e_side cb_ipin_side = cb_ipin_sides[iside];
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side);
++inode) {
std::vector<RREdgeId> driver_rr_edges =
rr_gsb.get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode);
for (const RREdgeId curr_edge : driver_rr_edges) {
RRNodeId cand_node = rr_graph.edge_src_node(curr_edge);
if (OPIN != rr_graph.node_type(cand_node);
continue;
}
if (opin_rr_nodes.end() == std::find(opin_rr_nodes.begin(), opin_rr_nodes.end(), cand_node)) {
opin_rr_nodes.push_back(cand_node);
}
}
}
}
std::vector<ModulePortId> opin_module_port_ids;
for (const RRNodeId& opin_node : opin_rr_nodes) {
enum e_side cb_opin_side = NUM_SIDES;
int cb_opin_index = -1;
rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side,
cb_opin_index);
VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side));
std::string port_name = generate_cb_module_grid_port_name(
cb_opin_side, grids, device_annotation, rr_graph, opin_node);
BasicPort module_port(port_name,
1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
ModulePortId module_port_id = module_manager.add_port(
cb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(cb_module, module_port_id, cb_opin_side);
opin_module_port_ids.push_back(module_port_id);
}
/* Create a cache (fast look up) for module nets whose source are input ports
*/
std::map<ModulePinInfo, ModuleNetId> input_port_to_module_nets;
@ -1034,6 +1072,17 @@ static void build_connection_block_module(
chan_lower_input_port_id, chan_lower_input_port.pins()[pin_id])] = net;
}
for (ModulePortId opin_module_port_id : opin_module_port_ids) {
ModuleNetId net = create_module_source_pin_net(
module_manager, cb_module, cb_module, 0, opin_module_port_id,
0);
module_manager.add_module_net_sink(cb_module, net, cb_module, 0,
opin_module_port_id,
0);
/* Cache the module net */
input_port_to_module_nets[ModulePinInfo(opin_module_port_id, 0)] = net;
}
/* Add sub modules of routing multiplexers or direct interconnect*/
for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
enum e_side cb_ipin_side = cb_ipin_sides[iside];