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[core] adding pin side attribute to module manager

This commit is contained in:
tangxifan 2024-04-10 16:19:28 -07:00
parent 0af0ededd9
commit d156de060e
3 changed files with 40 additions and 1 deletions
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30
openfpga/src/fabric/module_manager.cpp
View File

@ -304,6 +304,19 @@ std::vector<BasicPort> ModuleManager::module_ports_by_type(
return ports;
}
e_side ModuleManager::pin_side(
const ModuleId& module_id, const ModulePortId& port_id, const size_t& pin_id) const {
VTR_ASSERT(valid_module_port_id(module_id, port_id));
BasicPort curr_port = module_manager.module_port(module_id, port_id);
BasicPort curr_pin(curr_port.get_name(), pin_id, pin_id);
/* Not a valid pin id, return invalid side */
if (!curr_port.contained(curr_pin)) {
return NUM_SIDES;
}
/* Reach here, return a valid value */
return port_sides_[module_id][port_id][pin_id]
}
/* Find a list of port ids of a module by a given types */
std::vector<ModulePortId> ModuleManager::module_port_ids_by_type(
const ModuleId& module_id, const enum e_module_port_type& port_type) const {
@ -789,6 +802,8 @@ ModulePortId ModuleManager::add_port(const ModuleId& module,
port_ids_[module].push_back(port);
ports_[module].push_back(port_info);
port_types_[module].push_back(port_type);
/* Deposit invalid value for each side */
port_sides_[module].push_back(std::vector<e_side>(port_info.get_width(), NUM_SIDES));
port_is_wire_[module].push_back(false);
port_is_mappable_io_[module].push_back(false);
port_is_register_[module].push_back(false);
@ -893,6 +908,21 @@ void ModuleManager::set_port_preproc_flag(const ModuleId& module,
port_preproc_flags_[module][port] = preproc_flag;
}
/* Set the side for a pin of a port port */
void ModuleManager::set_pin_side(const ModuleId& module,
const ModulePortId& port,
const size_t& pin,
const e_side& pin_side) {
/* Must find something, otherwise drop an error */
VTR_ASSERT(valid_module_port_id(module, port));
if (pin > port_sides_[module][port].size() - 1) {
VTR_LOG_ERROR("Invalid pin '%ld' for module '%s' port '%s'!\n", pin, module_name(module).c_str(), module_port(module, port).to_verilog_string().c_str());
VTR_ASSERT(pin < port_sides_[module][port].size());
}
port_sides_[module][port][pin] = pin_side;
}
/* Add a child module to a parent module */
void ModuleManager::add_child_module(const ModuleId& parent_module,
const ModuleId& child_module,

9
openfpga/src/fabric/module_manager.h
View File

@ -273,6 +273,10 @@ class ModuleManager {
/* Find the type of a port */
ModuleManager::e_module_port_type port_type(const ModuleId& module,
const ModulePortId& port) const;
/* Get the physical side of a pin of a port. Note that not every pin has a valid side. An invalid value NUM_SIDES will be returned when the pin does not has a specific physical location */
e_side pin_side(const ModuleId& module,
const ModulePortId& port,
const size_t& pin_id) const;
/* Find if a port is a wire connection */
bool port_is_wire(const ModuleId& module, const ModulePortId& port) const;
/* Find if a port is mappable to an I/O from users' implementations */
@ -369,6 +373,9 @@ class ModuleManager {
/* Set the preprocessing flag for a port */
void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port,
const std::string& preproc_flag);
/* Set side to a given pin of a module port. Note that the pin id must be a valid one. Otherwise, abort and error out. The valid pin range can be get from module_port().pins() */
void set_pin_side(const ModuleId& module, const ModulePortId& port,
const size_t& pin, const e_side& pin_side);
/** @brief Add a child module to a parent module.
* By default, it considers the child module as an I/O child, and update the
* children list of I/O modules inside It not needed, just turn it off. Then
@ -626,6 +633,8 @@ class ModuleManager {
ports_; /* List of ports for each Module */
vtr::vector<ModuleId, vtr::vector<ModulePortId, enum e_module_port_type>>
port_types_; /* Type of ports */
vtr::vector<ModuleId, vtr::vector<ModulePortId, std::vector<e_side>>>
port_sides_; /* Type of ports */
vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_mappable_io_; /* If the port is mappable to an I/O for user's
implementations */

2
openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp
View File

@ -66,7 +66,7 @@ static int write_xml_fabric_module_pin_phy_loc(
for (int curr_pin_id : curr_port.pins()) {
BasicPort curr_pin(curr_port.get_name(), curr_pin_id, curr_pin_id);
std::string curr_port_str = generate_xml_port_name(curr_pin);
SideManager side_mgr(module_manager.module_pin_side(curr_module, curr_port_id, curr_pin_id));
SideManager side_mgr(module_manager.pin_side(curr_module, curr_port_id, curr_pin_id));
write_tab_to_file(fp, 2);
fp << "<" << XML_MODULE_PINLOC_NODE_NAME;
write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_PIN, curr_port_str.c_str());