riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] syntax

This commit is contained in:
tangxifan 2024-05-18 22:17:52 -07:00
parent b533ea4060
commit 304f34525e
4 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -359,14 +359,15 @@ ModulePortId find_connection_block_module_opin_port(
********************************************************************/
std::vector<ModulePinInfo> find_connection_block_module_input_ports(
const ModuleManager& module_manager, const ModuleId& cb_module,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<ModulePinInfo> input_ports;
for (auto input_rr_node : input_rr_nodes) {
if (OPIN == rr_graph.node_type(input_rr_node)) {
input_ports.push_back(find_connection_block_module_opin_port(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));
input_ports.push_back(ModulePinInfo(find_connection_block_module_opin_port(
module_manager, cb_module, grids, vpr_device_annotation, rr_graph, rr_gsb, input_rr_node), 0));
} else {
input_ports.push_back(find_connection_block_module_chan_port(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));

1
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -70,6 +70,7 @@ ModulePortId find_connection_block_module_opin_port(
std::vector<ModulePinInfo> find_connection_block_module_input_ports(
const ModuleManager& module_manager, const ModuleId& cb_module,
const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation,
const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes);

6
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -692,7 +692,7 @@ static void build_connection_block_mux_module(
* multiplexer */
std::vector<ModulePinInfo> cb_input_port_ids =
find_connection_block_module_input_ports(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports =
@ -1003,7 +1003,7 @@ static void build_connection_block_module(
rr_gsb.get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode);
for (const RREdgeId curr_edge : driver_rr_edges) {
RRNodeId cand_node = rr_graph.edge_src_node(curr_edge);
if (OPIN != rr_graph.node_type(cand_node);
if (OPIN != rr_graph.node_type(cand_node)) {
continue;
}
if (opin_rr_nodes.end() == std::find(opin_rr_nodes.begin(), opin_rr_nodes.end(), cand_node)) {
@ -1016,7 +1016,7 @@ static void build_connection_block_module(
for (const RRNodeId& opin_node : opin_rr_nodes) {
enum e_side cb_opin_side = NUM_SIDES;
int cb_opin_index = -1;
rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, IN_PORT, cb_opin_side,
rr_gsb.get_node_side_and_index(rr_graph, opin_node, IN_PORT, cb_opin_side,
cb_opin_index);
VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side));
std::string port_name = generate_cb_module_grid_port_name(

2
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -318,7 +318,7 @@ static void print_pnr_sdc_constrain_cb_mux_timing(
* rr_node */
std::vector<ModulePinInfo> module_input_ports =
find_connection_block_module_input_ports(
module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_nodes);
module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, cb_type, input_rr_nodes);
/* Find timing constraints for each path (edge) */
std::map<ModulePinInfo, float> switch_delays;