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[core] update vtr and developing caches for OPIN lists just for connection blocks

This commit is contained in:
tangxifan 2024-05-19 14:10:00 -07:00
parent 772da3006b
commit 918bf79ca3
4 changed files with 21 additions and 41 deletions
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3
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -398,6 +398,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
temp_ipin_rr_nodes.clear();
}
/* Build OPIN node lists for connection blocks */
rr_gsb.build_cb_opin_nodes(vpr_device_ctx.rr_graph);
return rr_gsb;
}

3
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -330,9 +330,6 @@ ModulePortId find_connection_block_module_opin_port(
const RRNodeId& src_rr_node) {
/* Ensure the src_rr_node is an input pin of a CLB */
VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node));
/* Create port description for input pin of a CLB */
vtr::Point<size_t> port_coord(rr_graph.node_xlow(src_rr_node),
rr_graph.node_ylow(src_rr_node));
/* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB
*/
enum e_side cb_opin_side = NUM_SIDES;

54
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -980,8 +980,6 @@ static void build_connection_block_module(
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side);
++inode) {
RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
vtr::Point<size_t> port_coord(rr_graph.node_xlow(ipin_node),
rr_graph.node_ylow(ipin_node));
std::string port_name = generate_cb_module_grid_port_name(
cb_ipin_side, grids, device_annotation, rr_graph, ipin_node);
BasicPort module_port(port_name,
@ -996,42 +994,24 @@ static void build_connection_block_module(
/* Add the output pins of grids which are input ports of the connection block,
* if there is any */
std::vector<RRNodeId> opin_rr_nodes;
for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) {
enum e_side cb_ipin_side = cb_ipin_sides[iside];
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side);
++inode) {
std::vector<RREdgeId> driver_rr_edges =
rr_gsb.get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode);
for (const RREdgeId curr_edge : driver_rr_edges) {
RRNodeId cand_node = rr_graph.edge_src_node(curr_edge);
if (OPIN != rr_graph.node_type(cand_node)) {
continue;
}
if (opin_rr_nodes.end() ==
std::find(opin_rr_nodes.begin(), opin_rr_nodes.end(), cand_node)) {
opin_rr_nodes.push_back(cand_node);
}
}
}
}
std::vector<ModulePortId> opin_module_port_ids;
for (const RRNodeId& opin_node : opin_rr_nodes) {
enum e_side cb_opin_side = NUM_SIDES;
int cb_opin_index = -1;
rr_gsb.get_node_side_and_index(rr_graph, opin_node, IN_PORT, cb_opin_side,
cb_opin_index);
VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side));
std::string port_name = generate_cb_module_grid_port_name(
cb_opin_side, grids, device_annotation, rr_graph, opin_node);
BasicPort module_port(port_name,
1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
ModulePortId module_port_id = module_manager.add_port(
cb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(cb_module, module_port_id, cb_opin_side);
opin_module_port_ids.push_back(module_port_id);
std::vector<enum e_side> cb_opin_sides = rr_gsb.get_cb_opin_sides(cb_type);
for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) {
enum e_side cb_opin_side = cb_opin_sides[iside];
for (size_t inode = 0; inode < rr_gsb.get_num_cb_opin_nodes(cb_opin_side);
++inode) {
RRNodeId opin_node = rr_gsb.get_cb_opin_node(cb_opin_side, inode);
std::string port_name = generate_cb_module_grid_port_name(
cb_opin_side, grids, device_annotation, rr_graph, opin_node);
BasicPort module_port(port_name,
1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
ModulePortId module_port_id = module_manager.add_port(
cb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(cb_module, module_port_id, cb_opin_side);
opin_module_port_ids.push_back(module_port_id);
}
}
/* Create a cache (fast look up) for module nets whose source are input ports

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 26bac8cbac6b0140aee84c30dc2683506c1073cb
Subproject commit 7b78e57ec9609086d13a450bd325ac0767fa7987