From 918bf79ca32a49c03a68a3253a144ad2e41a93eb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 19 May 2024 14:10:00 -0700 Subject: [PATCH] [core] update vtr and developing caches for OPIN lists just for connection blocks --- openfpga/src/annotation/annotate_rr_graph.cpp | 3 ++ .../src/fabric/build_routing_module_utils.cpp | 3 -- openfpga/src/fabric/build_routing_modules.cpp | 54 ++++++------------- vtr-verilog-to-routing | 2 +- 4 files changed, 21 insertions(+), 41 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 3a904aefd..7dc1d7c72 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -398,6 +398,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, temp_ipin_rr_nodes.clear(); } + /* Build OPIN node lists for connection blocks */ + rr_gsb.build_cb_opin_nodes(vpr_device_ctx.rr_graph); + return rr_gsb; } diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index f075a06a3..b8f9b4c0d 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -330,9 +330,6 @@ ModulePortId find_connection_block_module_opin_port( const RRNodeId& src_rr_node) { /* Ensure the src_rr_node is an input pin of a CLB */ VTR_ASSERT(OPIN == rr_graph.node_type(src_rr_node)); - /* Create port description for input pin of a CLB */ - vtr::Point port_coord(rr_graph.node_xlow(src_rr_node), - rr_graph.node_ylow(src_rr_node)); /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ enum e_side cb_opin_side = NUM_SIDES; diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp index 6c9457475..952e97cf5 100644 --- a/openfpga/src/fabric/build_routing_modules.cpp +++ b/openfpga/src/fabric/build_routing_modules.cpp @@ -980,8 +980,6 @@ static void build_connection_block_module( for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { RRNodeId ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); - vtr::Point port_coord(rr_graph.node_xlow(ipin_node), - rr_graph.node_ylow(ipin_node)); std::string port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, device_annotation, rr_graph, ipin_node); BasicPort module_port(port_name, @@ -996,42 +994,24 @@ static void build_connection_block_module( /* Add the output pins of grids which are input ports of the connection block, * if there is any */ - std::vector opin_rr_nodes; - for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { - enum e_side cb_ipin_side = cb_ipin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); - ++inode) { - std::vector driver_rr_edges = - rr_gsb.get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); - for (const RREdgeId curr_edge : driver_rr_edges) { - RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); - if (OPIN != rr_graph.node_type(cand_node)) { - continue; - } - if (opin_rr_nodes.end() == - std::find(opin_rr_nodes.begin(), opin_rr_nodes.end(), cand_node)) { - opin_rr_nodes.push_back(cand_node); - } - } - } - } std::vector opin_module_port_ids; - for (const RRNodeId& opin_node : opin_rr_nodes) { - enum e_side cb_opin_side = NUM_SIDES; - int cb_opin_index = -1; - rr_gsb.get_node_side_and_index(rr_graph, opin_node, IN_PORT, cb_opin_side, - cb_opin_index); - VTR_ASSERT((-1 != cb_opin_index) && (NUM_SIDES != cb_opin_side)); - std::string port_name = generate_cb_module_grid_port_name( - cb_opin_side, grids, device_annotation, rr_graph, opin_node); - BasicPort module_port(port_name, - 1); /* Every grid output has a port size of 1 */ - /* Grid outputs are inputs of switch blocks */ - ModulePortId module_port_id = module_manager.add_port( - cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); - /* Add side to the port */ - module_manager.set_port_side(cb_module, module_port_id, cb_opin_side); - opin_module_port_ids.push_back(module_port_id); + std::vector cb_opin_sides = rr_gsb.get_cb_opin_sides(cb_type); + for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { + enum e_side cb_opin_side = cb_opin_sides[iside]; + for (size_t inode = 0; inode < rr_gsb.get_num_cb_opin_nodes(cb_opin_side); + ++inode) { + RRNodeId opin_node = rr_gsb.get_cb_opin_node(cb_opin_side, inode); + std::string port_name = generate_cb_module_grid_port_name( + cb_opin_side, grids, device_annotation, rr_graph, opin_node); + BasicPort module_port(port_name, + 1); /* Every grid output has a port size of 1 */ + /* Grid outputs are inputs of switch blocks */ + ModulePortId module_port_id = module_manager.add_port( + cb_module, module_port, ModuleManager::MODULE_INPUT_PORT); + /* Add side to the port */ + module_manager.set_port_side(cb_module, module_port_id, cb_opin_side); + opin_module_port_ids.push_back(module_port_id); + } } /* Create a cache (fast look up) for module nets whose source are input ports diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 26bac8cba..7b78e57ec 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 26bac8cbac6b0140aee84c30dc2683506c1073cb +Subproject commit 7b78e57ec9609086d13a450bd325ac0767fa7987