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[core] syntax

This commit is contained in:
tangxifan 2024-04-10 20:08:02 -07:00
parent 435e83c530
commit 58708ff727
9 changed files with 32 additions and 25 deletions
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3
openfpga/src/base/openfpga_build_fabric_template.h
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@ -449,12 +449,11 @@ int write_fabric_pin_physical_location_template(const T& openfpga_ctx,
/* Write hierarchy to a file */
return write_xml_fabric_pin_physical_location(
file_name.c_str(), module_name,
openfpga_ctx.module_name_map(), openfpga_ctx.module_graph(),
openfpga_ctx.module_graph(),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
}
} /* end namespace openfpga */
#endif

14
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
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@ -123,8 +123,10 @@ void add_grid_module_duplicated_pb_type_ports(
}
BasicPort grid_port(port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_port,
ModulePortId grid_port_id = module_manager.add_port(grid_module, grid_port,
pin_type2type_map[pin_class_type]);
/* Set port side */
module_manager.set_port_side(grid_module, grid_port_id, side);
} else {
/* For each DRIVER pin, we create two copies.
* One with a postfix of upper, indicating it is located on the
@ -136,18 +138,20 @@ void add_grid_module_duplicated_pb_type_ports(
iwidth, iheight, subtile_index, side, pin_info, true);
BasicPort grid_upper_port(upper_port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_upper_port,
ModulePortId grid_upper_port_id = module_manager.add_port(grid_module, grid_upper_port,
pin_type2type_map[pin_class_type]);
/* Set port side */
module_manager.set_port_side(grid_module, grid_upper_port_id, side);
std::string lower_port_name = generate_grid_duplicated_port_name(
iwidth, iheight, subtile_index, side, pin_info, false);
BasicPort grid_lower_port(lower_port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_lower_port,
ModulePortId grid_lower_port_id = module_manager.add_port(grid_module, grid_lower_port,
pin_type2type_map[pin_class_type]);
/* Set port side */
module_manager.set_port_side(grid_module, grid_lower_port_id, side);
}
/* Set port side */
module_manager.set_port_side(grid_module, grid_port, side);
}
}
}

4
openfpga/src/fabric/build_grid_modules.cpp
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@ -103,10 +103,10 @@ static void add_grid_module_pb_type_ports(
}
BasicPort grid_port(port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_port,
ModulePortId grid_port_id = module_manager.add_port(grid_module, grid_port,
pin_type2type_map[pin_class_type]);
/* Set port side */
module_manager.set_port_side(grid_module, grid_port, side);
module_manager.set_port_side(grid_module, grid_port_id, side);
}
}
}

10
openfpga/src/fabric/build_routing_modules.cpp
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@ -436,7 +436,7 @@ static void build_switch_block_module(
ModulePortId chan_input_port_id = module_manager.add_port(
sb_module, chan_input_port, ModuleManager::MODULE_INPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(sb_module, chan_input_port_id, side_manager.get_side())
module_manager.set_port_side(sb_module, chan_input_port_id, side_manager.get_side());
/* Cache the input net */
for (const size_t& pin : chan_input_port.pins()) {
@ -451,7 +451,7 @@ static void build_switch_block_module(
ModulePortId chan_output_port_id = module_manager.add_port(sb_module, chan_output_port,
ModuleManager::MODULE_OUTPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(sb_module, chan_output_port_id, side_manager.get_side())
module_manager.set_port_side(sb_module, chan_output_port_id, side_manager.get_side());
}
/* Dump OPINs of adjacent CLBs */
@ -473,7 +473,7 @@ static void build_switch_block_module(
ModulePortId input_port_id = module_manager.add_port(
sb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(sb_module, module_port, side_manager.get_side())
module_manager.set_port_side(sb_module, input_port_id, side_manager.get_side());
/* Cache the input net */
ModuleNetId net = create_module_source_pin_net(
@ -979,10 +979,10 @@ static void build_connection_block_module(
BasicPort module_port(port_name,
1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
module_manager.add_port(cb_module, module_port,
ModulePortId module_port_id = module_manager.add_port(cb_module, module_port,
ModuleManager::MODULE_OUTPUT_PORT);
/* Add side to the port */
module_manager.set_port_side(cb_module, module_port, cb_ipin_side)
module_manager.set_port_side(cb_module, module_port_id, cb_ipin_side);
}
}

2
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -744,7 +744,7 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
tile_module, chan_output_port,
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT);
/* Set port side, inherit from the child module */
module_manager.set_port_side(tile_module, tile_chan_output_port_id, module_manager.port_side(sb_module_id, src_chan_output_port_id));
module_manager.set_port_side(tile_module, tile_chan_output_port_id, module_manager.port_side(sb_module_id, sb_chan_output_port_id));
VTR_LOGV(
verbose,
"Adding ports '%s' to tile as required by the switch block '%s'...\n",

4
openfpga/src/fabric/module_manager.cpp
View File

@ -307,7 +307,7 @@ std::vector<BasicPort> ModuleManager::module_ports_by_type(
e_side ModuleManager::port_side(
const ModuleId& module_id, const ModulePortId& port_id) const {
VTR_ASSERT(valid_module_port_id(module_id, port_id));
return port_sides_[module_id][port_id]
return port_sides_[module_id][port_id];
}
/* Find a list of port ids of a module by a given types */
@ -902,7 +902,7 @@ void ModuleManager::set_port_preproc_flag(const ModuleId& module,
}
/* Set the side for a pin of a port port */
void ModuleManager::set_pin_side(const ModuleId& module,
void ModuleManager::set_port_side(const ModuleId& module,
const ModulePortId& port,
const e_side& pin_side) {
/* Must find something, otherwise drop an error */

1
openfpga/src/fabric/module_manager.h
View File

@ -7,6 +7,7 @@
#include <unordered_map>
#include <unordered_set>
#include "physical_types.h"
#include "module_manager_fwd.h"
#include "openfpga_port.h"
#include "vtr_geometry.h"

17
openfpga/src/fabric/write_xml_fabric_pin_physical_location.cpp
View File

@ -14,6 +14,7 @@
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_side_manager.h"
#include "command_exit_codes.h"
/* Headers from arch openfpga library */
@ -71,7 +72,7 @@ static int write_xml_fabric_module_pin_phy_loc(
fp << "<" << XML_MODULE_PINLOC_NODE_NAME;
write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_PIN, curr_port_str.c_str());
write_xml_attribute(fp, XML_MODULE_PINLOC_ATTRIBUTE_SIDE, side_mgr.c_str());
fp << "/>"
fp << "/>";
fp << std::endl;
}
}
@ -90,7 +91,7 @@ static int write_xml_fabric_module_pin_phy_loc(
*******************************************************************/
int write_xml_fabric_pin_physical_location(
const char* fname, const std::string& module_name,
const ModuleGraph& module_manager,
const ModuleManager& module_manager,
const bool& include_time_stamp,
const bool& verbose) {
@ -112,11 +113,11 @@ int write_xml_fabric_pin_physical_location(
<< "\n";
/* If module name is not specified, walk through all the modules and write physical pin location when any is specified */
cnt = 0;
short cnt = 0;
if (module_name.empty()) {
for (ModuleId curr_module : module_manager.modules()) {
int err_code = write_xml_fabric_module_pin_phy_loc(fp, curr_module);
if (err_code != CMD_EXEC_SUCESS) {
int err_code = write_xml_fabric_module_pin_phy_loc(fp, module_manager, curr_module);
if (err_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
cnt++;
@ -129,8 +130,8 @@ int write_xml_fabric_pin_physical_location(
return CMD_EXEC_FATAL_ERROR;
}
/* Write the pin physical location for this module */
int err_code = write_xml_fabric_module_pin_phy_loc(fp, curr_module);
if (err_code != CMD_EXEC_SUCESS) {
int err_code = write_xml_fabric_module_pin_phy_loc(fp, module_manager, curr_module);
if (err_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
cnt++;
@ -146,4 +147,6 @@ int write_xml_fabric_pin_physical_location(
VTR_LOGV(verbose, "Outputted %lu modules with pin physical location.\n", cnt);
return CMD_EXEC_SUCCESS;
}
} /* end namespace openfpga */

2
openfpga/src/fabric/write_xml_fabric_pin_physical_location.h
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@ -17,7 +17,7 @@ namespace openfpga {
int write_xml_fabric_pin_physical_location(
const char* fname, const std::string& module_name,
const ModuleGraph& module_manager,
const ModuleManager& module_manager,
const bool& include_time_stamp,
const bool& verbose);