[core] code format
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@ -66,11 +66,18 @@ std::vector<size_t> ConfigProtocol::prog_clock_pin_ccff_head_indices(
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VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
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std::vector<size_t> ret;
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if (port.get_width() != 1) {
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VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
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VTR_LOG_ERROR(
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"The programming clock pin must have a width of 1 while the width "
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"specified is %ld!\n",
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port.get_width());
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}
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VTR_ASSERT(port.get_width() == 1);
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if (!prog_clk_port_.contained(port)) {
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VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
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VTR_LOG_ERROR(
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"The programming clock pin '%s[%ld]' is not out of the range [%ld, "
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"%ld]!\n",
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port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(),
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prog_clk_port_.get_msb());
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}
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VTR_ASSERT(prog_clk_port_.contained(port));
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return prog_clk_ccff_head_indices_[port.get_lsb()];
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@ -138,11 +145,18 @@ void ConfigProtocol::set_prog_clock_pin_ccff_head_indices_pair(
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token_int.push_back(std::stoi(token));
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}
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if (port.get_width() != 1) {
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VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
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VTR_LOG_ERROR(
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"The programming clock pin must have a width of 1 while the width "
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"specified is %ld!\n",
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port.get_width());
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}
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VTR_ASSERT(port.get_width() == 1);
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if (!prog_clk_port_.contained(port)) {
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VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
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VTR_LOG_ERROR(
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"The programming clock pin '%s[%ld]' is not out of the range [%ld, "
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"%ld]!\n",
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port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(),
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prog_clk_port_.get_msb());
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}
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VTR_ASSERT(prog_clk_port_.contained(port));
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if (!prog_clk_ccff_head_indices_[port.get_lsb()].empty()) {
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@ -31,11 +31,13 @@ class ConfigProtocol {
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CircuitModelId memory_model() const;
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int num_regions() const;
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/* Find the number of programming clocks, only valid for configuration chain type! */
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/* Find the number of programming clocks, only valid for configuration chain
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* type! */
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size_t num_prog_clocks() const;
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/* Get information of the programming clock port: name and width */
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openfpga::BasicPort prog_clock_port_info() const;
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/* Get a list of programming clock pins, flatten from the programming clock port */
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/* Get a list of programming clock pins, flatten from the programming clock
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* port */
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std::vector<openfpga::BasicPort> prog_clock_pins() const;
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/* Get a list of programming clock ports */
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std::string prog_clock_pin_ccff_head_indices_str(
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@ -67,8 +67,7 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
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openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
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config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port,
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indices_attr);
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config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port, indices_attr);
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}
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/********************************************************************
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@ -187,11 +186,12 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
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/* Error out if the XML child has an invalid name! */
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if (xml_progclk.name() !=
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std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
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bad_tag(xml_progclk, loc_data, xml_config_orgz, {XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
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bad_tag(xml_progclk, loc_data, xml_config_orgz,
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{XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
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}
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std::string port_attr =
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get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
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loc_data)
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get_attribute(xml_progclk,
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XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, loc_data)
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.as_string();
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openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
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if (prog_clk_port.get_name().empty()) {
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@ -200,7 +200,10 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
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} else {
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if (prog_clk_port.get_name() != port.get_name()) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_progclk),
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"Expect same name for all the programming clocks (This: %s, Others: %s)!\n", port.get_name().c_str(), prog_clk_port.get_name().c_str());
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"Expect same name for all the programming clocks "
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"(This: %s, Others: %s)!\n",
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port.get_name().c_str(),
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prog_clk_port.get_name().c_str());
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}
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if (prog_clk_port.get_msb() < port.get_msb()) {
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prog_clk_port.set_msb(port.get_msb());
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@ -214,7 +217,8 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
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/* Error out if the XML child has an invalid name! */
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if (xml_progclk.name() !=
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std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
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bad_tag(xml_progclk, loc_data, xml_config_orgz, {XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
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bad_tag(xml_progclk, loc_data, xml_config_orgz,
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{XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
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}
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read_xml_ccff_prog_clock(xml_progclk, loc_data, config_protocol);
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}
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@ -595,7 +595,8 @@ int build_top_module(
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}
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}
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/* For configuration chains, we avoid adding nets for programmable clocks if there are a few */
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/* For configuration chains, we avoid adding nets for programmable clocks if
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* there are a few */
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std::vector<std::string> global_port_blacklist;
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if (config_protocol.num_prog_clocks() > 1) {
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BasicPort prog_clk_port = config_protocol.prog_clock_port_info();
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@ -604,7 +605,8 @@ int build_top_module(
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ModulePortId port_id = module_manager.add_port(
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top_module, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT);
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/* Add nets by following configurable children under different regions */
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add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol);
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add_top_module_nets_prog_clock(module_manager, top_module, port_id,
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config_protocol);
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}
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/* Add global ports to the top module:
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@ -614,7 +616,8 @@ int build_top_module(
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* @note This function is called after the
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* add_top_module_nets_memory_config_bus() because it may add some sub modules
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*/
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add_module_global_ports_from_child_modules(module_manager, top_module, global_port_blacklist);
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add_module_global_ports_from_child_modules(module_manager, top_module,
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global_port_blacklist);
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return status;
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}
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@ -1270,9 +1270,9 @@ int add_top_module_global_ports_from_grid_modules(
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}
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/********************************************************************
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* Build the connection between the programming clock port at the top module and each configurable children
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* Note that each programming clock pin drive one or more configuration regions
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* For example:
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* Build the connection between the programming clock port at the top module and
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*each configurable children Note that each programming clock pin drive one or
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*more configuration regions For example:
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* - pin[0] -> region 0, 1
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* - pin[1] -> region 2, 3
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*******************************************************************/
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@ -1284,31 +1284,34 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager,
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for (size_t net_src_pin_id : src_port_info.pins()) {
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/* Create the net */
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ModuleNetId net = create_module_source_pin_net(
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module_manager, top_module, top_module, 0,
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src_port, src_port_info.pins()[net_src_pin_id]);
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module_manager, top_module, top_module, 0, src_port,
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src_port_info.pins()[net_src_pin_id]);
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/* Find all the sink nodes and build the connection one by one */
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for (size_t iregion : config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) {
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for (size_t iregion :
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config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(
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src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) {
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ConfigRegionId config_region = ConfigRegionId(iregion);
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for (size_t mem_index = 0; mem_index < module_manager
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.region_configurable_children(
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top_module, config_region)
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.size();
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++mem_index) {
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ModuleId net_sink_module_id = module_manager.region_configurable_children(
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top_module, config_region)[mem_index];
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ModuleId net_sink_module_id =
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module_manager.region_configurable_children(top_module,
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config_region)[mem_index];
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size_t net_sink_instance_id =
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module_manager.region_configurable_child_instances(
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top_module, config_region)[mem_index];
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ModulePortId net_sink_port_id =
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module_manager.find_module_port(net_sink_module_id, src_port_info.get_name());
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ModulePortId net_sink_port_id = module_manager.find_module_port(
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net_sink_module_id, src_port_info.get_name());
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BasicPort net_sink_port =
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module_manager.module_port(net_sink_module_id, net_sink_port_id);
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VTR_ASSERT(1 == net_sink_port.get_width());
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for (size_t net_sink_pin_id : net_sink_port.pins()) {
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/* Add net sink */
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module_manager.add_module_net_sink(top_module, net, net_sink_module_id,
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net_sink_instance_id, net_sink_port_id,
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net_sink_port.pins()[net_sink_pin_id]);
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module_manager.add_module_net_sink(
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top_module, net, net_sink_module_id, net_sink_instance_id,
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net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]);
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}
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}
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}
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@ -6,8 +6,8 @@
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*******************************************************************/
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#include <vector>
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#include "config_protocol.h"
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#include "clock_network.h"
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#include "config_protocol.h"
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#include "device_grid.h"
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#include "device_rr_gsb.h"
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#include "module_manager.h"
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@ -2185,7 +2185,8 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
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* Otherwise, some global ports of the sub modules may be missed!
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*******************************************************************/
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void add_module_global_input_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id, const std::vector<std::string>& port_name_to_ignore) {
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore) {
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std::vector<BasicPort> global_ports_to_add;
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/* Iterate over the child modules */
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@ -2205,7 +2206,8 @@ void add_module_global_input_ports_from_child_modules(
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/* Reach here, this is an unique global port, update the list
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* Final check: ignore those in the blacklist
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*/
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if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(), global_port.get_name()) == port_name_to_ignore.end()) {
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if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(),
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global_port.get_name()) == port_name_to_ignore.end()) {
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global_ports_to_add.push_back(global_port);
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}
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}
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@ -2307,11 +2309,12 @@ void add_module_global_input_ports_from_child_modules(
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* have been added to the pb_module!
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* Otherwise, some global ports of the sub modules may be missed!
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*******************************************************************/
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void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
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const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore) {
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void add_module_global_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore) {
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/* Input ports */
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add_module_global_input_ports_from_child_modules(module_manager, module_id, port_name_to_ignore);
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add_module_global_input_ports_from_child_modules(module_manager, module_id,
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port_name_to_ignore);
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}
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/********************************************************************
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@ -148,14 +148,16 @@ size_t find_module_num_config_bits(
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void add_module_global_input_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
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const std::vector<std::string>& port_name_to_ignore =
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std::vector<std::string>());
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void add_module_global_output_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id);
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void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
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const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
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void add_module_global_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore =
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std::vector<std::string>());
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void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
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const ModuleId& module_id);
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