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[core] code format

This commit is contained in:
tangxifan 2023-04-23 14:31:35 +08:00
parent bd511ba515
commit 28b7a12f68
8 changed files with 71 additions and 40 deletions
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22
libs/libarchopenfpga/src/config_protocol.cpp
View File

@ -66,11 +66,18 @@ std::vector<size_t> ConfigProtocol::prog_clock_pin_ccff_head_indices(
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
std::vector<size_t> ret;
if (port.get_width() != 1) {
VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
VTR_LOG_ERROR(
"The programming clock pin must have a width of 1 while the width "
"specified is %ld!\n",
port.get_width());
}
VTR_ASSERT(port.get_width() == 1);
if (!prog_clk_port_.contained(port)) {
VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
VTR_LOG_ERROR(
"The programming clock pin '%s[%ld]' is not out of the range [%ld, "
"%ld]!\n",
port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(),
prog_clk_port_.get_msb());
}
VTR_ASSERT(prog_clk_port_.contained(port));
return prog_clk_ccff_head_indices_[port.get_lsb()];
@ -138,11 +145,18 @@ void ConfigProtocol::set_prog_clock_pin_ccff_head_indices_pair(
token_int.push_back(std::stoi(token));
}
if (port.get_width() != 1) {
VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
VTR_LOG_ERROR(
"The programming clock pin must have a width of 1 while the width "
"specified is %ld!\n",
port.get_width());
}
VTR_ASSERT(port.get_width() == 1);
if (!prog_clk_port_.contained(port)) {
VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
VTR_LOG_ERROR(
"The programming clock pin '%s[%ld]' is not out of the range [%ld, "
"%ld]!\n",
port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(),
prog_clk_port_.get_msb());
}
VTR_ASSERT(prog_clk_port_.contained(port));
if (!prog_clk_ccff_head_indices_[port.get_lsb()].empty()) {

6
libs/libarchopenfpga/src/config_protocol.h
View File

@ -31,11 +31,13 @@ class ConfigProtocol {
CircuitModelId memory_model() const;
int num_regions() const;
/* Find the number of programming clocks, only valid for configuration chain type! */
/* Find the number of programming clocks, only valid for configuration chain
* type! */
size_t num_prog_clocks() const;
/* Get information of the programming clock port: name and width */
openfpga::BasicPort prog_clock_port_info() const;
/* Get a list of programming clock pins, flatten from the programming clock port */
/* Get a list of programming clock pins, flatten from the programming clock
* port */
std::vector<openfpga::BasicPort> prog_clock_pins() const;
/* Get a list of programming clock ports */
std::string prog_clock_pin_ccff_head_indices_str(

18
libs/libarchopenfpga/src/read_xml_config_protocol.cpp
View File

@ -67,8 +67,7 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port,
indices_attr);
config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port, indices_attr);
}
/********************************************************************
@ -187,11 +186,12 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
/* Error out if the XML child has an invalid name! */
if (xml_progclk.name() !=
std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
bad_tag(xml_progclk, loc_data, xml_config_orgz, {XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
bad_tag(xml_progclk, loc_data, xml_config_orgz,
{XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
}
std::string port_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
loc_data)
get_attribute(xml_progclk,
XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, loc_data)
.as_string();
openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
if (prog_clk_port.get_name().empty()) {
@ -200,7 +200,10 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
} else {
if (prog_clk_port.get_name() != port.get_name()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_progclk),
"Expect same name for all the programming clocks (This: %s, Others: %s)!\n", port.get_name().c_str(), prog_clk_port.get_name().c_str());
"Expect same name for all the programming clocks "
"(This: %s, Others: %s)!\n",
port.get_name().c_str(),
prog_clk_port.get_name().c_str());
}
if (prog_clk_port.get_msb() < port.get_msb()) {
prog_clk_port.set_msb(port.get_msb());
@ -214,7 +217,8 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
/* Error out if the XML child has an invalid name! */
if (xml_progclk.name() !=
std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
bad_tag(xml_progclk, loc_data, xml_config_orgz, {XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
bad_tag(xml_progclk, loc_data, xml_config_orgz,
{XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME});
}
read_xml_ccff_prog_clock(xml_progclk, loc_data, config_protocol);
}

9
openfpga/src/fabric/build_top_module.cpp
View File

@ -595,7 +595,8 @@ int build_top_module(
}
}
/* For configuration chains, we avoid adding nets for programmable clocks if there are a few */
/* For configuration chains, we avoid adding nets for programmable clocks if
* there are a few */
std::vector<std::string> global_port_blacklist;
if (config_protocol.num_prog_clocks() > 1) {
BasicPort prog_clk_port = config_protocol.prog_clock_port_info();
@ -604,7 +605,8 @@ int build_top_module(
ModulePortId port_id = module_manager.add_port(
top_module, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT);
/* Add nets by following configurable children under different regions */
add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol);
add_top_module_nets_prog_clock(module_manager, top_module, port_id,
config_protocol);
}
/* Add global ports to the top module:
@ -614,7 +616,8 @@ int build_top_module(
* @note This function is called after the
* add_top_module_nets_memory_config_bus() because it may add some sub modules
*/
add_module_global_ports_from_child_modules(module_manager, top_module, global_port_blacklist);
add_module_global_ports_from_child_modules(module_manager, top_module,
global_port_blacklist);
return status;
}

29
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -1270,9 +1270,9 @@ int add_top_module_global_ports_from_grid_modules(
}
/********************************************************************
* Build the connection between the programming clock port at the top module and each configurable children
* Note that each programming clock pin drive one or more configuration regions
* For example:
* Build the connection between the programming clock port at the top module and
*each configurable children Note that each programming clock pin drive one or
*more configuration regions For example:
* - pin[0] -> region 0, 1
* - pin[1] -> region 2, 3
*******************************************************************/
@ -1284,31 +1284,34 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager,
for (size_t net_src_pin_id : src_port_info.pins()) {
/* Create the net */
ModuleNetId net = create_module_source_pin_net(
module_manager, top_module, top_module, 0,
src_port, src_port_info.pins()[net_src_pin_id]);
module_manager, top_module, top_module, 0, src_port,
src_port_info.pins()[net_src_pin_id]);
/* Find all the sink nodes and build the connection one by one */
for (size_t iregion : config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) {
for (size_t iregion :
config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(
src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) {
ConfigRegionId config_region = ConfigRegionId(iregion);
for (size_t mem_index = 0; mem_index < module_manager
.region_configurable_children(
top_module, config_region)
.size();
++mem_index) {
ModuleId net_sink_module_id = module_manager.region_configurable_children(
top_module, config_region)[mem_index];
ModuleId net_sink_module_id =
module_manager.region_configurable_children(top_module,
config_region)[mem_index];
size_t net_sink_instance_id =
module_manager.region_configurable_child_instances(
top_module, config_region)[mem_index];
ModulePortId net_sink_port_id =
module_manager.find_module_port(net_sink_module_id, src_port_info.get_name());
ModulePortId net_sink_port_id = module_manager.find_module_port(
net_sink_module_id, src_port_info.get_name());
BasicPort net_sink_port =
module_manager.module_port(net_sink_module_id, net_sink_port_id);
VTR_ASSERT(1 == net_sink_port.get_width());
for (size_t net_sink_pin_id : net_sink_port.pins()) {
/* Add net sink */
module_manager.add_module_net_sink(top_module, net, net_sink_module_id,
net_sink_instance_id, net_sink_port_id,
net_sink_port.pins()[net_sink_pin_id]);
module_manager.add_module_net_sink(
top_module, net, net_sink_module_id, net_sink_instance_id,
net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]);
}
}
}

2
openfpga/src/fabric/build_top_module_connection.h
View File

@ -6,8 +6,8 @@
*******************************************************************/
#include <vector>
#include "config_protocol.h"
#include "clock_network.h"
#include "config_protocol.h"
#include "device_grid.h"
#include "device_rr_gsb.h"
#include "module_manager.h"

15
openfpga/src/utils/module_manager_utils.cpp
View File

@ -2185,7 +2185,8 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
* Otherwise, some global ports of the sub modules may be missed!
*******************************************************************/
void add_module_global_input_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id, const std::vector<std::string>& port_name_to_ignore) {
ModuleManager& module_manager, const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore) {
std::vector<BasicPort> global_ports_to_add;
/* Iterate over the child modules */
@ -2205,7 +2206,8 @@ void add_module_global_input_ports_from_child_modules(
/* Reach here, this is an unique global port, update the list
* Final check: ignore those in the blacklist
*/
if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(), global_port.get_name()) == port_name_to_ignore.end()) {
if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(),
global_port.get_name()) == port_name_to_ignore.end()) {
global_ports_to_add.push_back(global_port);
}
}
@ -2307,11 +2309,12 @@ void add_module_global_input_ports_from_child_modules(
* have been added to the pb_module!
* Otherwise, some global ports of the sub modules may be missed!
*******************************************************************/
void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore) {
void add_module_global_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore) {
/* Input ports */
add_module_global_input_ports_from_child_modules(module_manager, module_id, port_name_to_ignore);
add_module_global_input_ports_from_child_modules(module_manager, module_id,
port_name_to_ignore);
}
/********************************************************************

10
openfpga/src/utils/module_manager_utils.h
View File

@ -148,14 +148,16 @@ size_t find_module_num_config_bits(
void add_module_global_input_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
const std::vector<std::string>& port_name_to_ignore =
std::vector<std::string>());
void add_module_global_output_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id);
void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
void add_module_global_ports_from_child_modules(
ModuleManager& module_manager, const ModuleId& module_id,
const std::vector<std::string>& port_name_to_ignore =
std::vector<std::string>());
void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
const ModuleId& module_id);