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[core] now adapt to latest API of DeviceGrid

This commit is contained in:
tangxifan 2023-06-07 18:54:48 -07:00
parent 46640d3965
commit 327f7f4dab
14 changed files with 97 additions and 94 deletions
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2
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -396,7 +396,7 @@ static void try_find_and_add_clock_track2ipin_node(
const e_side& pin_side, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type =
grids[grid_coord.x()][grid_coord.y()].type;
grids.get_physical_type(grid_coord.x(), grid_coord.y());
for (std::string tap_pin_name :
clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */

2
openfpga/src/annotation/vpr_placement_annotation.cpp
View File

@ -32,7 +32,7 @@ void VprPlacementAnnotation::init_mapped_blocks(const DeviceGrid& grids) {
for (size_t x = 0; x < grids.width(); ++x) {
for (size_t y = 0; y < grids.height(); ++y) {
/* Deposit invalid ids and we will fill later */
blocks_[x][y].resize(grids[x][y].type->capacity,
blocks_[x][y].resize(grids.get_physical_type(x, y)->capacity,
ClusterBlockId::INVALID());
}
}

7
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -39,7 +39,7 @@ static void update_cluster_pin_with_post_routing_results(
const e_side& border_side, const size_t& z, const bool& verbose) {
/* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
auto physical_tile = device_ctx.grid[grid_coord.x()][grid_coord.y()].type;
auto physical_tile = device_ctx.grid.get_physical_type(grid_coord.x(), grid_coord.y());
for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
/* Get the ptc num for the pin in rr_graph, we need t consider the z offset
@ -195,7 +195,7 @@ void update_pb_pin_with_post_routing_results(
for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
/* Bypass the EMPTY tiles */
if (true == is_empty_type(device_ctx.grid[x][y].type)) {
if (true == is_empty_type(device_ctx.grid.get_physical_type(x, y))) {
continue;
}
/* Get the mapped blocks to this grid */
@ -222,9 +222,10 @@ void update_pb_pin_with_post_routing_results(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type = device_ctx.grid.get_physical_type(io_coord.x(), io_coord.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(device_ctx.grid[io_coord.x()][io_coord.y()].type)) {
is_empty_type(phy_tile_type)) {
continue;
}
/* Get the mapped blocks to this grid */

15
openfpga/src/fabric/build_fabric_io_location_map.cpp
View File

@ -50,15 +50,16 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
ModuleId child = module_manager.io_children(top_module)[ichild];
vtr::Point<int> coord =
module_manager.io_child_coordinates(top_module)[ichild];
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(coord.x(), coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[coord.x()][coord.y()].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[coord.x()][coord.y()].width_offset) ||
(0 < grids[coord.x()][coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(coord.x(), coord.y())) ||
(0 < grids.get_height_offset(coord.x(), coord.y()))) {
continue;
}
@ -69,14 +70,14 @@ IoLocationMap build_fabric_io_location_map(const ModuleManager& module_manager,
/* MUST DO: register in io location mapping!
* I/O location mapping is a critical look-up for testbench generators
*/
if (size_t(grids[coord.x()][coord.y()].type->capacity) !=
if (size_t(phy_tile_type->capacity) !=
module_manager.io_children(child).size()) {
VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
grids[coord.x()][coord.y()].type->name, coord.x(), coord.y(),
grids[coord.x()][coord.y()].type->capacity,
phy_tile_type->name, coord.x(), coord.y(),
phy_tile_type->capacity,
module_manager.io_children(child).size());
}
VTR_ASSERT(size_t(grids[coord.x()][coord.y()].type->capacity) ==
VTR_ASSERT(size_t(phy_tile_type->capacity) ==
module_manager.io_children(child).size());
for (size_t isubchild = 0;
isubchild < module_manager.io_children(child).size(); ++isubchild) {

6
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -77,8 +77,7 @@ std::string generate_sb_module_grid_port_name(
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile =
vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]
.type;
vpr_device_grid.get_physical_type(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =
@ -112,8 +111,7 @@ std::string generate_cb_module_grid_port_name(
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = get_rr_graph_single_node_side(rr_graph, rr_node);
t_physical_tile_type_ptr physical_tile =
vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)]
.type;
vpr_device_grid.get_physical_type(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node));
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info =

43
openfpga/src/fabric/build_top_module.cpp
View File

@ -108,22 +108,23 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(io_coordinate.x(), io_coordinate.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 < grids.get_height_offset(io_coordinate.x(),io_coordinate.y()))) {
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_grid_coord(
io_coordinate.x() -
grids[io_coordinate.x()][io_coordinate.y()].width_offset,
grids.get_width_offset(io_coordinate.x(), io_coordinate.y()),
io_coordinate.y() -
grids[io_coordinate.x()][io_coordinate.y()].height_offset);
grids.get_height_offset(io_coordinate.x(), io_coordinate.y()));
VTR_ASSERT(size_t(-1) !=
grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
grid_instance_ids[io_coordinate.x()][io_coordinate.y()] =
@ -135,7 +136,7 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
grid_instance_ids[io_coordinate.x()][io_coordinate.y()] =
add_top_module_grid_instance(
module_manager, top_module,
grids[io_coordinate.x()][io_coordinate.y()].type, io_side,
phy_tile_type, io_side,
io_coordinate);
}
}
@ -148,18 +149,19 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
*/
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy);
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
/* Find the root of this grid, the instance id should be valid.
* We just copy it here
*/
vtr::Point<size_t> root_grid_coord(ix - grids[ix][iy].width_offset,
iy - grids[ix][iy].height_offset);
vtr::Point<size_t> root_grid_coord(ix - grids.get_width_offset(ix, iy),
iy - grids.get_height_offset(ix, iy));
VTR_ASSERT(size_t(-1) !=
grid_instance_ids[root_grid_coord.x()][root_grid_coord.y()]);
grid_instance_ids[ix][iy] =
@ -169,7 +171,7 @@ static vtr::Matrix<size_t> add_top_module_grid_instances(
/* Add a grid module to top_module*/
vtr::Point<size_t> grid_coord(ix, iy);
grid_instance_ids[ix][iy] = add_top_module_grid_instance(
module_manager, top_module, grids[ix][iy].type, NUM_SIDES, grid_coord);
module_manager, top_module, phy_tile_type, NUM_SIDES, grid_coord);
}
}
@ -324,18 +326,17 @@ static void add_top_module_io_children(
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(io_coord.x(), io_coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[io_coord.x()][io_coord.y()].type)) {
if (true == is_empty_type(grid_type)) {
continue;
}
/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coord.x()][io_coord.y()].width_offset) ||
(0 < grids[io_coord.x()][io_coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coord.x(), io_coord.y())) ||
(0 < grids.get_height_offset(io_coord.x(), io_coord.y()))) {
continue;
}
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type =
grids[io_coord.x()][io_coord.y()].type;
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
grid_module_name_prefix, std::string(grid_type->name),
@ -393,17 +394,17 @@ static void add_top_module_io_children(
/* Now walk through the coordinates */
for (vtr::Point<size_t> coord : coords) {
t_physical_tile_type_ptr grid_type = grids.get_physical_type(coord.x(), coord.y());
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[coord.x()][coord.y()].type)) {
if (true == is_empty_type(grid_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[coord.x()][coord.y()].width_offset) ||
(0 < grids[coord.x()][coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(coord.x(), coord.y())) ||
(0 < grids.get_height_offset(coord.x(), coord.y()))) {
continue;
}
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type = grids[coord.x()][coord.y()].type;
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
grid_module_name_prefix, std::string(grid_type->name),

26
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -127,7 +127,7 @@ static void add_top_module_nets_connect_grids_and_sb(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -301,7 +301,7 @@ static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(
rr_gsb.get_opin_node(side_manager.get_side(), inode));
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t src_grid_pin_width =
grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height =
@ -520,7 +520,7 @@ static void add_top_module_nets_connect_grids_and_cb(
size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
t_physical_tile_type_ptr grid_type_descriptor =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
size_t sink_grid_pin_width =
grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height =
@ -859,7 +859,7 @@ static int build_top_module_global_net_for_given_grid_module(
const vtr::Point<size_t>& grid_coordinate, const e_side& border_side,
const vtr::Matrix<size_t>& grid_instance_ids) {
t_physical_tile_type_ptr physical_tile =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
/* Find the module name for this type of grid */
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
std::string grid_module_name = generate_grid_block_module_name(
@ -1038,18 +1038,19 @@ static int build_top_module_global_net_from_grid_modules(
/* Spot the port from child modules from core grids */
for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) {
for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(ix, iy);
/* Bypass EMPTY tiles */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
continue;
}
/* Bypass the tiles whose names do not match */
if (std::string(grids[ix][iy].type->name) != tile_name) {
if (std::string(phy_tile_type->name) != tile_name) {
continue;
}
@ -1067,21 +1068,22 @@ static int build_top_module_global_net_from_grid_modules(
/* Walk through all the grids on the perimeter, which are I/O grids */
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(io_coordinate.x(), io_coordinate.y());
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
is_empty_type(phy_tile_type)) {
continue;
}
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
/* Bypass the tiles whose names do not match */
if (std::string(
grids[io_coordinate.x()][io_coordinate.y()].type->name) !=
phy_tile_type->name) !=
tile_name) {
continue;
}

8
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -47,7 +47,7 @@ static void add_module_nets_tile_direct_connection(
vtr::Point<size_t> src_clb_coord =
tile_direct.from_tile_coordinate(tile_direct_id);
t_physical_tile_type_ptr src_grid_type =
grids[src_clb_coord.x()][src_clb_coord.y()].type;
grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y());
e_side src_grid_border_side =
find_grid_border_side(device_size, src_clb_coord);
std::string src_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -64,7 +64,7 @@ static void add_module_nets_tile_direct_connection(
vtr::Point<size_t> des_clb_coord =
tile_direct.to_tile_coordinate(tile_direct_id);
t_physical_tile_type_ptr sink_grid_type =
grids[des_clb_coord.x()][des_clb_coord.y()].type;
grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y());
e_side sink_grid_border_side =
find_grid_border_side(device_size, des_clb_coord);
std::string sink_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -114,7 +114,7 @@ static void add_module_nets_tile_direct_connection(
size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id);
t_physical_tile_type_ptr src_grid_type_descriptor =
grids[src_clb_coord.x()][src_clb_coord.y()].type;
grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y());
size_t src_pin_width =
src_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t src_pin_height =
@ -148,7 +148,7 @@ static void add_module_nets_tile_direct_connection(
size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id);
t_physical_tile_type_ptr sink_grid_type_descriptor =
grids[des_clb_coord.x()][des_clb_coord.y()].type;
grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y());
size_t sink_pin_width =
sink_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t sink_pin_height =

6
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -191,7 +191,7 @@ static void organize_top_module_tile_memory_modules(
/* Find the module name for this type of grid */
t_physical_tile_type_ptr grid_type =
grids[tile_coord.x()][tile_coord.y()].type;
grids.get_physical_type(tile_coord.x(), tile_coord.y());
/* Skip EMPTY Grid */
if (true == is_empty_type(grid_type)) {
@ -199,8 +199,8 @@ static void organize_top_module_tile_memory_modules(
}
/* Skip width > 1 or height > 1 Grid, which should already been processed when
* offset=0 */
if ((0 < grids[tile_coord.x()][tile_coord.y()].width_offset) ||
(0 < grids[tile_coord.x()][tile_coord.y()].height_offset)) {
if ((0 < grids.get_width_offset(tile_coord.x(), tile_coord.y())) ||
(0 < grids.get_height_offset(tile_coord.x(), tile_coord.y()))) {
return;
}

5
openfpga/src/fabric/build_top_module_utils.cpp
View File

@ -28,10 +28,11 @@ std::string generate_grid_block_module_name_in_top_module(
/* Determine if the grid locates at the border */
vtr::Point<size_t> device_size(grids.width(), grids.height());
e_side border_side = find_grid_border_side(device_size, grid_coord);
t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(grid_coord.x(), grid_coord.y());
return generate_grid_block_module_name(
prefix, std::string(grids[grid_coord.x()][grid_coord.y()].type->name),
is_io_type(grids[grid_coord.x()][grid_coord.y()].type), border_side);
prefix, std::string(phy_tile_type->name),
is_io_type(phy_tile_type), border_side);
}
/********************************************************************

14
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -736,7 +736,7 @@ static void build_physical_block_bitstream(
const vtr::Point<size_t>& grid_coord, const e_side& border_side) {
/* Create a block for the grid in bitstream manager */
t_physical_tile_type_ptr grid_type =
grids[grid_coord.x()][grid_coord.y()].type;
grids.get_physical_type(grid_coord.x(), grid_coord.y());
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
/* Early exit if this parent module has no configurable child modules */
@ -831,12 +831,12 @@ void build_grid_bitstream(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
/* Bypass EMPTY grid */
if (true == is_empty_type(grids[ix][iy].type)) {
if (true == is_empty_type(grids.get_physical_type(ix, iy))) {
continue;
}
/* Skip width > 1 or height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[ix][iy].width_offset) ||
(0 < grids[ix][iy].height_offset)) {
if ((0 < grids.get_width_offset(ix, iy)) ||
(0 < grids.get_height_offset(ix, iy))) {
continue;
}
/* Add a grid module to top_module*/
@ -860,12 +860,12 @@ void build_grid_bitstream(
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
/* Bypass EMPTY grid */
if (true ==
is_empty_type(grids[io_coordinate.x()][io_coordinate.y()].type)) {
is_empty_type(grids.get_physical_type(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
/* Skip height > 1 tiles (mostly heterogeneous blocks) */
if ((0 < grids[io_coordinate.x()][io_coordinate.y()].width_offset) ||
(0 < grids[io_coordinate.x()][io_coordinate.y()].height_offset)) {
if ((0 < grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
(0 < grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
continue;
}
build_physical_block_bitstream(

6
openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
View File

@ -604,14 +604,14 @@ static void print_analysis_sdc_disable_unused_grid(
valid_file_stream(fp);
t_physical_tile_type_ptr grid_type =
grids[grid_coordinate.x()][grid_coordinate.y()].type;
grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
/* Bypass conditions for grids :
* 1. EMPTY type, which is by nature unused
* 2. Offset > 0, which has already been processed when offset = 0
*/
if ((true == is_empty_type(grid_type)) ||
(0 < grids[grid_coordinate.x()][grid_coordinate.y()].width_offset) ||
(0 < grids[grid_coordinate.x()][grid_coordinate.y()].height_offset)) {
(0 < grids.get_width_offset(grid_coordinate.x(), grid_coordinate.y())) ||
(0 < grids.get_height_offset(grid_coordinate.x(), grid_coordinate.y()))) {
return;
}

47
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -168,7 +168,7 @@ static vtr::Point<size_t> find_grid_coordinate_given_type(
continue;
}
if (wanted_grid_type_name ==
std::string(grids[coord.x()][coord.y()].type->name)) {
std::string(grids.get_physical_type(coord.x(), coord.y())->name)) {
return coord;
}
}
@ -401,13 +401,14 @@ static void build_inner_column_row_tile_direct(
/* Walk through the device fabric and find the grid that fit the source */
for (size_t x = 0; x < device_ctx.grid.width(); ++x) {
for (size_t y = 0; y < device_ctx.grid.height(); ++y) {
t_physical_tile_type_ptr from_phy_tile_type = device_ctx.grid.get_physical_type(x, y);
/* Bypass empty grid */
if (true == is_empty_type(device_ctx.grid[x][y].type)) {
if (true == is_empty_type(from_phy_tile_type)) {
continue;
}
/* Bypass the grid that does not fit the from_tile name */
if (from_tile_name != std::string(device_ctx.grid[x][y].type->name)) {
if (from_tile_name != std::string(from_phy_tile_type->name)) {
continue;
}
@ -418,8 +419,8 @@ static void build_inner_column_row_tile_direct(
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[x][y].type, device_ctx.grid[x][y].width_offset,
device_ctx.grid[x][y].height_offset, from_tile_port, from_side);
from_phy_tile_type, device_ctx.grid.get_width_offset(x, y),
device_ctx.grid.get_height_offset(x, y), from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
continue;
@ -435,10 +436,10 @@ static void build_inner_column_row_tile_direct(
continue;
}
t_physical_tile_type_ptr to_phy_tile_type = device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y());
/* Bypass the grid that does not fit the from_tile name */
if (to_tile_name !=
std::string(device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()]
.type->name)) {
std::string(to_phy_tile_type->name)) {
continue;
}
@ -449,9 +450,9 @@ static void build_inner_column_row_tile_direct(
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
to_phy_tile_type,
device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
@ -590,11 +591,9 @@ static void build_inter_column_row_tile_direct(
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()]
.width_offset,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()]
.height_offset,
device_ctx.grid.get_physical_type(from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_width_offset(from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_height_offset(from_grid_coord.x(), from_grid_coord.y()),
from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
@ -620,9 +619,9 @@ static void build_inter_column_row_tile_direct(
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {
@ -699,9 +698,9 @@ static void build_inter_column_row_tile_direct(
for (const e_side& from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> from_pins = find_physical_tile_pin_id(
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].type,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].width_offset,
device_ctx.grid[from_grid_coord.x()][from_grid_coord.y()].height_offset,
device_ctx.grid.get_physical_type(from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_width_offset(from_grid_coord.x(), from_grid_coord.y()),
device_ctx.grid.get_height_offset(from_grid_coord.x(), from_grid_coord.y()),
from_tile_port, from_side);
/* If nothing found, we can continue */
if (0 == from_pins.size()) {
@ -727,9 +726,9 @@ static void build_inter_column_row_tile_direct(
for (const e_side& to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
/* Try to find the pin in this tile */
std::vector<size_t> to_pins = find_physical_tile_pin_id(
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].type,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].width_offset,
device_ctx.grid[to_grid_coord.x()][to_grid_coord.y()].height_offset,
device_ctx.grid.get_physical_type(to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_width_offset(to_grid_coord.x(), to_grid_coord.y()),
device_ctx.grid.get_height_offset(to_grid_coord.x(), to_grid_coord.y()),
to_tile_port, to_side);
/* If nothing found, we can continue */
if (0 == to_pins.size()) {

4
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -89,7 +89,7 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile == grids[ix][iy].type) {
if (physical_tile == grids.get_physical_type(ix, iy)) {
io_sides.insert(NUM_SIDES);
center_io = true;
break;
@ -108,7 +108,7 @@ std::set<e_side> find_physical_io_tile_located_sides(
for (const e_side& fpga_side : FPGA_SIDES_CLOCKWISE) {
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[fpga_side]) {
/* If located in center, we add a NUM_SIDES and finish */
if (physical_tile == grids[io_coordinate.x()][io_coordinate.y()].type) {
if (physical_tile == grids.get_physical_type(io_coordinate.x(), io_coordinate.y())) {
io_sides.insert(fpga_side);
break;
}