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1360 Commits

Author SHA1 Message Date
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam 
Fixes #1822.
 2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 06a344efcb ilang, ast: Store parameter order and default value information. 
Fixes #1819, #1820.
 2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 79efaa65ad idict: Make iterator go forward. 
Previously, iterating over an idict returned its contents in reverse.
 2020-04-21 19:09:00 +02:00
Alberto Gonzalez ecaa892e35
Add rvalue-reference-accepting `entry_t` constructor for `pool`. 2020-04-20 05:37:10 +00:00
Alberto Gonzalez 95b94ad19b
In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding `insert()` method. 2020-04-20 02:18:30 +00:00
whitequark b6f624b56b rtlil: add AttrObject::has_attribute. 2020-04-16 21:49:49 +00:00
whitequark ff7a1a1568 rtlil: add AttrObject::{get,set}_string_attribute. 
And make {get,set}_src_attribute use those functions.
 2020-04-16 21:45:29 +00:00
whitequark c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl 
Frontend: allow reading file input from stdin, like a REPL heredoc mode
 2020-04-16 17:18:29 +00:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert 
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
 2020-04-16 08:06:12 -07:00
whitequark 90a1c6b6a4
Merge pull request #1915 from boqwxp/dict_move_semantics 
kernel: Add `dict` support for rvalue references and C++11 move semantics.
 2020-04-16 13:29:13 +00:00
Alberto Gonzalez 5eb1f83d2d
Rename overloaded `insert()` to `emplace()` and add overloaded versions for all possible lvalue/rvalue combinationsfor its arguments. 2020-04-16 03:54:33 +00:00
Alberto Gonzalez 76c9e1c265
Use script-style heredoc syntax for REPL heredocs. 2020-04-15 16:15:51 +00:00
Alberto Gonzalez b5ecbbef94
Allow reading file input from stdin, improving REPL experience. 2020-04-15 16:15:50 +00:00
Miodrag Milanović 3c4758c60e
Merge pull request #1894 from YosysHQ/mingw_fix 
Fix compile for mingw
 2020-04-15 17:43:31 +02:00
Eddie Hung dc3d432aaa
Merge pull request #1916 from YosysHQ/eddie/kernel_makeblackbox 
kernel: Module::makeblackbox() to clear connections too
 2020-04-15 08:42:39 -07:00
N. Engelhardt 0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat 
Add `qbfsat` command to integrate exists-forall solving and specialization
 2020-04-15 17:33:50 +02:00
Miodrag Milanovic bc21e58bb5 Fix compile for mingw 2020-04-15 16:38:09 +02:00
Eddie Hung 635b2b8939 kernel: Design::remove(RTLIL::Module *) to check refcount_modules_ 2020-04-14 09:31:06 -07:00
Eddie Hung 9547d8c13e kernel: Module::makeblackbox() to clear connections too 2020-04-13 20:37:22 -07:00
Alberto Gonzalez c479fdeb85
Add `dict` support for rvalue references and C++11 move semantics. 2020-04-13 23:52:16 +00:00
Miodrag Milanovic 0d789c5a3b Support custom PROGRAM_PREFIX 2020-04-10 10:38:40 +02:00
whitequark 7c06cb6157
Merge pull request #1562 from whitequark/write_cxxrtl 
write_cxxrtl: new backend
 2020-04-10 01:24:31 +00:00
Eddie Hung 371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856 
kernel: include "kernel/constids.inc"
 2020-04-09 14:23:47 -07:00
Eddie Hung 60ffc21e64 kernel: include "kernel/constids.inc" instead of "constids.inc" 2020-04-09 09:14:03 -07:00
Marcelina Kościelnicka 516857f3ba [NFCI] Deduplicate builtin FF cell types list 
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
 2020-04-09 18:05:06 +02:00
whitequark d20e971725 write_cxxrtl: new backend. 
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
 2020-04-09 04:08:36 +00:00
Alberto Gonzalez a4598d64ef
Hole value recovery and specialization implementation for `qbfsat` command. 2020-04-04 22:13:25 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung 2d86563bb2 kernel: IdString::in(const IdString &) as per @Tjoppen 2020-04-02 07:14:08 -07:00
Eddie Hung 18d85b88ae kernel: fix formatting (thanks @boqwxp) 2020-04-02 07:14:08 -07:00
Eddie Hung 7bcbf0c9d1 kernel: use C++11 fold hack to prevent recursion 2020-04-02 07:14:08 -07:00
Eddie Hung ba13a40ef4 Revert "kernel: IdString:in() to use perfect forwarding" 
This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
 2020-04-02 07:14:08 -07:00
Eddie Hung 6d4f01c3fa kernel: separate IdString::put_reference() out to help inlining 2020-04-02 07:14:08 -07:00
Eddie Hung 4a8cecf03e kernel: IdString:in() to use perfect forwarding 2020-04-02 07:14:08 -07:00
Eddie Hung 164dd0f6b2 kernel: Use constids.inc for global/constant IdStrings 2020-04-02 07:14:08 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup 
kernel: share a single CellTypes within a pass
 2020-04-01 14:17:45 -07:00
Alberto Gonzalez ae05795f54
Clean up pseudo-private member usage in `kernel/yosys.cc`. 2020-04-01 02:53:56 +00:00
Eddie Hung 348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Eddie Hung 6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Eddie Hung f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move 
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
 2020-03-26 14:33:06 -07:00
Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung 940640ac44 kernel: SigSpec copies to not trigger pack() 2020-03-18 11:51:00 -07:00
Eddie Hung 4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Eddie Hung 8b12e97153 kernel: speedup 2020-03-18 08:48:36 -07:00
Eddie Hung 8c45ea9f0e kernel: use const reference for SigSet too 2020-03-17 10:22:33 -07:00
Eddie Hung bc51e609cb kernel: fix DeleteWireWorker 2020-03-17 10:22:16 -07:00
Claire Wolf ed4fa19ba2 Update Copyright 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-16 16:28:25 +01:00
Waldir Pimenta 418c069561 License: bump year and add title 2020-03-14 16:46:07 +00:00
Miodrag Milanovic 395daf6ced exclude clang from checking 2020-03-13 17:23:27 +01:00
Miodrag Milanovic 8f221118d2 Add YS_ prefix to macros, add explanation and apply to older version as well 2020-03-13 17:19:54 +01:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
Miodrag Milanovic 7c54e61979 Use boost xpressive for gcc 4.8 2020-03-13 14:58:35 +01:00
Eddie Hung b567f03c26 kernel: optimise Module::remove(const pool<RTLIL::Wire*>() 2020-03-12 16:00:34 -07:00
Eddie Hung a076052fe4 kernel: SigPool to use const& + overloads to prevent implicit SigSpec 2020-03-12 16:00:34 -07:00
jiegec 7b679eecb3 Fix compilation for emcc 2020-03-11 22:09:24 +08:00
David Shah b8abf14376 Add ScriptPass::run_nocheck and use for abc9 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-09 14:34:22 +00:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Eddie Hung 0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00
Eddie Hung 78929e8c3d Fixes for older compilers 2020-02-27 10:17:29 -08:00
Eddie Hung 6bb3d9f9c0 Make TimingInfo::TimingInfo(SigBit) constructor explicit 2020-02-27 10:17:29 -08:00
Eddie Hung 9dcf204dec TimingInfo: index by (port_name,offset) 2020-02-27 10:17:29 -08:00
Eddie Hung 7c3b4b80ea Fix spacing 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung a6fec9fe60 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung 3ea5506f81 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung cda4acb544 abc9_ops: add and use new TimingInfo struct 2020-02-27 10:17:29 -08:00
Miodrag Milanović 036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass 
Logger pass
 2020-02-26 13:32:49 +01:00
Miodrag Milanovic 1c569fe06a Remove duplicate warning detection 2020-02-23 10:56:27 +01:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Miodrag Milanovic d079ab9d19 Handle expect no warnings together with expected 2020-02-22 10:52:46 +01:00
Miodrag Milanovic 70db8e9200 Prevent double error message 2020-02-17 16:46:34 +01:00
Miodrag Milanovic 5641b0248f Option to expect no warnings 2020-02-17 15:36:06 +01:00
Miodrag Milanovic be977cf7eb No new error if already failing 2020-02-17 12:54:36 +01:00
Miodrag Milanovic 6b396e6455 remove whitespace 2020-02-14 13:12:05 +01:00
Miodrag Milanovic 31b7a9c312 Add expect option to logger command 2020-02-14 12:21:16 +01:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Claire Wolf 5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental 
Add log_experimental() and experimental() API and "yosys -x"
 2020-01-29 15:25:03 +01:00
Eddie Hung 6d27d43727 Add and use SigSpec::reverse() 2020-01-28 10:37:16 -08:00
Claire Wolf 5c2508cef8 Improve logging use of experimental features 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-28 17:51:50 +01:00
Claire Wolf cef607c8b7 Add log_experimental() and experimental() API and "yosys -x" 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-27 18:27:47 +01:00
Claire Wolf de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias 
Add --version and -version as aliases for -V
 2020-01-27 12:59:27 +01:00
Eddie Hung ade57058f7 As before, only display MEM if Linux or FreeBSD 2020-01-14 11:38:48 -08:00
Eddie Hung a901a5fb44 print_stats footer to return peak memory, option for including children 2020-01-14 11:25:23 -08:00
Eddie Hung 67c9c41f7e Move abc9.* constpad entries to Abc9Pass::on_register() 2020-01-09 17:10:54 -08:00
Eddie Hung dd718838bb Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scratchpad 2020-01-09 17:06:13 -08:00
Clifford Wolf cd92a974f4 Add Pass::on_register() and Pass::on_shutdown() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2020-01-09 21:36:34 +01:00
Eddie Hung fbd9636e08 Add abc9.if.script.flow{,2} to constpad 2020-01-08 12:15:01 -08:00
Eddie Hung a63e2508fc Add RTLIL::constpad, init by yosys_setup(); use for abc9 2020-01-08 10:52:08 -08:00
Cassie Jones b76b023584 Add --version and -version as aliases for -V 
The flag --version is commonly accepted by command line tools.
The code for the version flags added here matches the pattern used for
the help flag aliases, for consistency.

Fixes #1612
 2020-01-05 03:19:02 -05:00
Clifford Wolf 3edb2e708b Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2020-01-02 18:58:45 +01:00
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
Eddie Hung 6bf7114bbd Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again 2019-10-04 16:45:36 -07:00
Eddie Hung 279fd22ddf Add Const::{begin,end,empty}() 2019-10-04 15:00:57 -07:00
Eddie Hung 62c66406ad log_dump() to support State enum 2019-10-02 17:49:07 -07:00
Eddie Hung d963e8c2c6 Fix typo 2019-09-30 15:18:40 -07:00
Miodrag Milanović 0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Eddie Hung d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map 
Avoid work in replace() if rules empty.
 2019-09-29 19:35:23 -07:00
Miodrag Milanovic 3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Henner Zeller 8c2b4f0a50 Avoid work in replace() if rules empty. 
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2019-09-29 00:17:40 -07:00
Miodrag Milanovic d0493925ec Support binary files for backends, fixes #1407 2019-09-28 09:36:18 +02:00
Miodrag Milanovic 435300f930 Make read/write gzip files on macos works, fixes #1357 2019-09-26 19:35:12 +02:00
Eddie Hung 9a84e4711c Spacing 2019-09-13 16:30:44 -07:00
Eddie Hung 5473e597bf Use template specialisation 2019-09-13 11:13:57 -07:00
Eddie Hung 95e80809a5 Revert "SigSet<Cell*> to use stable compare class" 
This reverts commit 4ea34aaacd.
 2019-09-13 09:49:15 -07:00
Eddie Hung c487a8ff25 Grammar 2019-09-12 12:00:34 -07:00
Eddie Hung c05a403dd1 static_assert to enforce this going forward 2019-09-12 11:45:17 -07:00
Eddie Hung 4ea34aaacd SigSet<Cell*> to use stable compare class 2019-09-12 11:45:02 -07:00
Clifford Wolf e9f3eb9760 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:16 +02:00
Clifford Wolf 2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255 
Fix various NDEBUG compiler warnings
 2019-08-17 15:07:16 +02:00
Eddie Hung 3b19c3657c Move namespace alias 2019-08-16 19:37:11 +00:00
Eddie Hung 0b9ee4fbbf Try this for gcc-4.8? 2019-08-15 16:20:54 -07:00
Eddie Hung 453a9429b6 Fix spacing 2019-08-15 14:54:41 -07:00
Eddie Hung 52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Clifford Wolf 49301b733e
Merge branch 'master' into clifford/fix1255 2019-08-15 22:44:38 +02:00
Eddie Hung 4cfefae21e More use of IdString::in() 2019-08-15 09:23:57 -07:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Clifford Wolf b25cf36856 Add YOSYS_NO_IDS_REFCNT configuration macro 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 12:23:16 +02:00
Clifford Wolf 390bf459fb Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf 8222c5735e More improvements and cleanups in IdString subsystem 
- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf b5534b66c8 Improve API of ID() macro 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 71eff6f0de RTLIL::S{0,1} -> State::S{0,1} for headers 2019-08-07 11:14:03 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Clifford Wolf 9260e97aa2 Automatically prune init attributes in verific front-end, fixes #1237 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 15:31:49 +02:00
Clifford Wolf e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
Clifford Wolf c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check 
Be less aggressive with running design->check()
 2019-08-07 12:14:41 +02:00
Clifford Wolf 338f6765eb Tweak default gate costs, cleanup "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 10:25:51 +02:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Eddie Hung 84f52aee0d Add SigSpec::extract_end() convenience function 2019-08-06 15:25:11 -07:00
Eddie Hung 0b56be8c56 Restore original SigSpec::extract() 2019-08-06 15:24:55 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
Clifford Wolf 95a6582f34 Be less aggressive with running design->check() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 19:21:37 +02:00
David Shah 27360ceda6 Add support for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Miodrag Milanovic f767179c75 New mxe hacks needed to support 2ca237e 2019-08-01 17:28:07 +02:00
Miodrag Milanovic 3e4307c104 Fix case when file does not exist 2019-07-29 12:29:13 +02:00
David Shah 6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip 
Add support for gzip'd input files
 2019-07-27 07:40:38 +01:00
David Shah da6701c4cd Fix frontend auto-detection for gzipped input 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:29:05 +01:00
David Shah 933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Jakob Wenzel 70882a8070 replaced std::iterator with using statements 2019-07-25 09:51:09 +02:00
Jakob Wenzel 25685a9a5b made ObjectIterator extend std::iterator 
this makes it possible to use std algorithms on them
 2019-07-24 16:35:40 +02:00
Eddie Hung 54708dfbd7 Add an SigSpec::at(offset, defval) convenience method 2019-07-19 13:54:57 -07:00
Eddie Hung 25ff27e37f SigSpec::extract to take negative lengths 2019-07-19 12:34:04 -07:00
Eddie Hung 06f94c92d4 Revert "Add log_checkpoint function and use it in opt_muxtree" 
This reverts commit 0e6c83027f.
 2019-07-15 08:35:48 -07:00
Clifford Wolf 44fd459c79 Redesign log_id_cache so that it doesn't keep IdString instances referenced, fixes #1178 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-15 17:10:42 +02:00
Clifford Wolf 0e6c83027f Add log_checkpoint function and use it in opt_muxtree 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-15 12:12:21 +02:00
Clifford Wolf ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs 
Allow attributes on individual switch cases in RTLIL
 2019-07-09 16:56:29 +02:00
Eddie Hung 41d7d9d24b Clarify script -scriptwire doc 2019-07-08 19:21:21 -07:00
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Eddie Hung f1504696e5 Use Pass::call_on_module() as per @cliffordwolf comments 2019-07-02 08:20:37 -07:00
Eddie Hung 02ba85b133 script -select -> script -scriptwire 2019-07-02 08:17:26 -07:00
Eddie Hung 06971385fa Support ability for "script -select" to take commands from wires 2019-06-28 13:36:33 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung fb30fcb7c5 Undo iterator based Module::remove() for cells, as containers will not 
invalidate
 2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic 0f32cb4e0a Merge remote-tracking branch 'upstream/master' 2019-06-27 12:11:47 +02:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Ben Widawsky 8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
whitequark df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky 468c41d997 Support ~ for home directory 
This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:38:40 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Bogdan Vukobratovic 8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic 53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Eddie Hung d09d4e0706 Move ConstEvalAig to aigerparse.cc 2019-06-13 16:28:11 -07:00
Eddie Hung 63e2f83632 More slimming 2019-06-13 13:29:03 -07:00
Eddie Hung d39a5a77a9 Add ConstEvalAig specialised for AIGs 2019-06-13 13:13:48 -07:00
Bogdan Vukobratovic 8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Bogdan Vukobratovic 4912567cbf Pass SigBit by value to Netlist algorithms 2019-06-13 15:42:45 +02:00
Bogdan Vukobratovic d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Eddie Hung f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Bogdan Vukobratovic 9892df17ef Generate satgen instance instead of calling sat pass 2019-06-11 11:47:13 +02:00
Bogdan Vukobratovic d097f423d1 Refactor driver map generation 
- Implement iterators over the driver map that enumerate signals and cells
  within the cones of the signal
 2019-06-10 21:42:35 +02:00
Clifford Wolf 211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Clifford Wolf 0971f772d7 Fix handling of warning and error messages within log_make_debug-blocks 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-22 13:46:38 +02:00
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:00 +02:00
Clifford Wolf 3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings 
Fix all warnings that occurred when compiling with gcc9
 2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch 30c762d3a1 Fix all warnings that occurred when compiling with gcc9 2019-05-08 10:27:14 +02:00
Clifford Wolf c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts 
Minor optimization to get_attribute_bool
 2019-05-08 08:34:35 +02:00
Matthew Daiter 6e629d2895 Minor optimization to get_attribute_bool 2019-05-07 22:04:28 -05:00
Matthew Daiter bafbb9ee90 Optimize ceil_log2 function 2019-05-07 12:17:56 -05:00
Clifford Wolf 87426f5a06 Improve write_verilog specify support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:46:24 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf 9268cd1613 Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:19:10 +02:00
Oleg Endo 4f15e7f00f fix codestyle formatting 2019-04-29 19:20:33 +09:00
Oleg Endo e531fb203a escape spaces with backslash when writing dep file 
filenames are sparated by spaces in the dep file.  if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
 2019-04-29 16:13:34 +09:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00
Clifford Wolf 4575e4ad86 Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:18:04 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e807e88b60 Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf aec2475a9d Add CellTypes support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf e1d73e03d3 Add InternalCellChecker support for $specify2 and $specify3 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 3cc95fb4be Add specify parser 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
David Shah 742c2f245d Fixes for OAI4 cell implementation 
Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-23 17:54:00 +01:00
Eddie Hung 2c6358ea25 Remove kernel/cost.cc since master has refactored it 2019-04-22 11:21:17 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Clifford Wolf 99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings 
Feature/python bindings
 2019-04-22 14:47:52 +02:00
Eddie Hung caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Clifford Wolf 5b915f0153 Add "wbflip" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:04:46 +02:00
Eddie Hung 290a798cec Ignore 'whitebox' attr in flatten with "-wb" option 2019-04-18 10:32:00 -07:00
Eddie Hung c997a77014 Ignore 'whitebox' attr in flatten with "-wb" option 2019-04-18 10:19:45 -07:00
Eddie Hung 8fe0a961b3 Merge remote-tracking branch 'origin/clifford/whitebox' into xaig 2019-04-18 09:00:06 -07:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung bca3cf6843 Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
Clifford Wolf dfb242c905 Add "read_ilang -lib" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-05 17:31:49 +02:00
Benedikt Tutzer 827a96d3a3 Global lists in rtlil.cc are now static objects 2019-04-03 14:27:39 +02:00
Benedikt Tutzer 0774a500d4 Added support for changing Yosys namespace 2019-04-03 12:21:21 +02:00
Benedikt Tutzer 072c939380 Fixed identation 2019-04-01 13:36:01 +02:00
Benedikt Tutzer 03d1606b42 Merge remote-tracking branch 'origin/master' into feature/python_bindings 2019-03-28 12:16:39 +01:00
Clifford Wolf 3b796c033c Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-23 14:38:48 +01:00
Clifford Wolf 370db33a4c Add fmcombine pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-15 20:46:17 +01:00
Clifford Wolf 76c9c350e7 Add hashlib "<container>::element(int n)" methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf 1cd04a6838 Fix a bug in handling quotes in multi-cmd lines in Yosys scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 21:15:11 +01:00
Clifford Wolf 20c6a8c9b0 Improve determinism of IdString DB for similar scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 20:12:28 +01:00
Clifford Wolf d9bb5f3637 Add ENABLE_GLOB Makefile switch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 01:08:36 -07:00
Eddie Hung f7c7003a19 Merge remote-tracking branch 'origin/master' into xaig 2019-02-26 13:16:03 -08:00
Eddie Hung 3ea0161ae7 Add IdString::ends_with() 2019-02-26 12:04:16 -08:00
Clifford Wolf c521f4632f
Merge pull request #819 from YosysHQ/clifford/optd 
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
 2019-02-22 06:55:48 +01:00
Eddie Hung a8803a1519 Merge remote-tracking branch 'origin/master' into xaig 2019-02-21 11:23:00 -08:00
Clifford Wolf 0a6588569b Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 15:51:59 +01:00
Clifford Wolf 953e0bf88d Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 14:27:46 +01:00
Clifford Wolf 246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
Eddie Hung edf7267019 Refactor kernel/cost.h definition into cost.cc 2019-02-08 13:58:20 -08:00
Clifford Wolf e70ebe557c Add optional nullstr argument to log_id() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:06:48 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark 18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
whitequark 2ca237e086 tcl: add support for passing arguments to scripts. 2018-12-20 07:32:24 +00:00
Clifford Wolf e90195b737 Improve ConstEval error handling for non-eval cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-29 05:07:40 +01:00
Jon Burgess 6732e56632 Avoid assert when label is an empty string 
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
 2018-10-28 14:57:04 +00:00
whentze 9ed77f5ba8 fix unhandled std::out_of_range when calling yosys with 3-character argument 2018-10-22 19:40:22 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc. 
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
 2018-10-13 20:34:44 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Adrian Wheeldon 1355492c89 Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00
Benedikt Tutzer 6f8abc1143 Exposed generator script to make-process 2018-09-19 10:32:34 +02:00
Miodrag Milanovic c5e9034834 Fix Cygwin build and document needed packages 2018-09-19 10:16:53 +02:00
Benedikt Tutzer 604734b484 added functions whose definitions are split over multiple lines 2018-08-23 14:48:20 +02:00
Benedikt Tutzer 586d7df7e2 added default yosys license text 2018-08-23 14:39:44 +02:00
Benedikt Tutzer ba18e0f81a Fixed segfault / multiple free issue with lists 2018-08-23 13:57:37 +02:00
Benedikt Tutzer 0ecfffa69c Do not pass heap object to Python. This way they should be completely managed by Python and destroyed when out of scope. Also, the file in which a function/struct was found is added to the comment before the function 2018-08-22 14:42:42 +02:00
Benedikt Tutzer 60608a86bb Fixed Identation 2018-08-22 11:59:22 +02:00
Benedikt Tutzer 038caab4e0 Wrapped functions that use unsigned int or type_t as types 2018-08-21 15:25:43 +02:00
Benedikt Tutzer 4acb29db0c added operators <, == and != 2018-08-21 14:49:35 +02:00
Benedikt Tutzer 334bfce4c4 Added previousely missed functions 2018-08-21 13:15:08 +02:00
Benedikt Tutzer 29efc9d0b1 Deleted duplicate Destructor 2018-08-21 11:07:59 +02:00
Benedikt Tutzer 95d65971f3 added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile 2018-08-20 16:04:43 +02:00
Benedikt Tutzer d41c68ee5a The share directory cannot be searched when used as a Python library, only in shell mode 2018-08-20 15:27:50 +02:00
Benedikt Tutzer 6d18837d62 Python passes are now looked for in share/plugins and can be added by specifying a relative or absolute path 2018-08-20 15:11:06 +02:00
Benedikt Tutzer 5864db3c2b Fixed issue when using a python plugin in the yosys shell 2018-08-20 14:44:03 +02:00
Benedikt Tutzer d79a2808cf Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script 2018-08-16 16:00:11 +02:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
litghost 80d7e007ff Map .eblif extension as blif. 
Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
 2018-08-13 14:02:53 -07:00
Benedikt Tutzer bf7b73acfc Added Wrappers for: 
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
 2018-08-13 15:18:46 +02:00
Benedikt Tutzer 416946a16a Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more 2018-08-01 10:57:57 +02:00
Benedikt Tutzer 79d7e608cf Setup is called automatically when the module is loaded, shutdown when python exits 2018-08-01 10:57:46 +02:00
Benedikt Tutzer 57d2197703 Cleaned up comments 2018-08-01 10:57:41 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller 1a60126a34 Provide source-location logging. 
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
 2018-07-19 10:22:02 -07:00
Benedikt Tutzer 0371519c39 Added Monitor class that can monitor all changes in a Design or in a Module 2018-07-10 12:51:02 +02:00
Benedikt Tutzer e7d3f3cd46 added destructors for wires and cells 2018-07-10 08:52:36 +02:00
Benedikt Tutzer 55df7fff19 removed debug output 2018-07-09 16:02:10 +02:00
Benedikt Tutzer da8083dbd0 commands can now be run on arbitrary designs, not only on the active one 2018-07-09 16:01:56 +02:00
Benedikt Tutzer 8ebaeecd83 multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues 2018-07-09 15:48:06 +02:00
Benedikt Tutzer 7911379d4a Introduced namespace and removed class-prefixes to increase readability 2018-06-28 15:07:21 +02:00
Benedikt Tutzer ccb4dcd013 changed references from hash-ids to IdString names 2018-06-28 14:44:28 +02:00
Benedikt Tutzer a27fa1833e added wrappers for Design, Modules, Cells and Wires 2018-06-25 17:08:29 +02:00
Robert Ou 0abe7c6c77 Modify emscripten main to mount nodefs and to run arg as a script 2018-05-18 22:53:52 -07:00
Robert Ou bd87462b47 Fix reading techlibs under emscripten 2018-05-18 22:42:33 -07:00
Christian Krämer c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf 1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Johnny Sorocil e3575a86c5 Add "#ifdef __FreeBSD__" 2018-05-05 13:02:44 +02:00
Clifford Wolf 5c03aeac60 Add "yosys -e regex" for turning warnings into errors 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-04 15:27:28 +02:00
Clifford Wolf 0acea3548b Set stack size to at least 128 MB (large stack needed for parsing huge expressions) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-27 15:04:10 +02:00
Edmond Cote 64ea55056a
Rename rename to renames 
Create TCL alias for rename command.  Using renames.  Following the same convention as proc -> procs.
 2018-03-20 15:50:50 -07:00
Larry Doolittle 82fecc98c0 Harmonize uses of _WIN32 macro 2018-03-11 16:01:30 +01:00
Clifford Wolf e5534a080e Improve handling of warning messages 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 22:35:59 +01:00
Clifford Wolf 2935e8ea41 Update copyright header 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-04 21:31:10 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf 82c436587c Do not create deep backtraces unless in ENABLE_DEBUG mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-03 15:04:39 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf c80315cea4 Bugfix in hierarchy handling of blackbox module ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-05 13:28:45 +01:00
Clifford Wolf 76afff7ef6 Add RTLIL::Const::is_fully_ones() 2017-12-14 02:06:39 +01:00
Clifford Wolf 96ad688849 Add SigSpec::is_fully_ones() 2017-12-14 01:29:09 +01:00
Kevin Kiningham 7350f7692a Use quote includes for yosys.h 2017-12-13 13:27:52 -08:00
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf 13eb47c692 Add src arguments to all cell creator helper functions 2017-09-09 10:16:48 +02:00
Clifford Wolf 8a66bd30c6 Update more stuff to use get_src_attribute() and set_src_attribute() 2017-09-01 12:26:55 +02:00
Jason Lowdermilk 71d43cfc08 Merge remote-tracking branch 'upstream/master' 2017-08-30 11:47:06 -06:00
Jason Lowdermilk 271e8ba7cd fix indent level 2017-08-30 11:46:41 -06:00
Clifford Wolf 8530333439 Add {get,set}_src_attribute() methods on RTLIL::AttrObject 2017-08-30 11:39:11 +02:00
Jason Lowdermilk 32c0f1193e Add support for source line tracking through synthesis phase 2017-08-29 14:46:35 -06:00
Clifford Wolf d3b3dd8e88 Add hashlib support for hashing of pools 2017-08-22 13:04:33 +02:00
Clifford Wolf bce0bb6e43 Add consteval support for $_ANDNOT_ and $_ORNOT_ 2017-08-22 13:04:05 +02:00
Clifford Wolf 4ba5bd12c6 Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() 2017-08-18 11:40:08 +02:00
Clifford Wolf 159701962a Auto-detect JSON front-end 2017-08-09 13:28:52 +02:00
Clifford Wolf 2336d5508b Add log_warning_noprefix() API, Use for Verific warnings and errors 2017-07-27 12:17:04 +02:00
Clifford Wolf 493fedbaf9 Add "using std::get" to yosys.h 2017-07-25 14:52:34 +02:00
Clifford Wolf c251e3a576 Change intptr_t to uintptr_t in hashlib.h 2017-07-18 17:38:19 +02:00
Robert Ou f0741698fa Fix build warnings for win64 
Win64 has a 32-bit long. Use intptr_t to work on any data model.
 2017-07-17 12:36:43 -07:00
Clifford Wolf 1f517d2b96 Fix history namespace collision 2017-06-20 05:26:12 +02:00
Clifford Wolf c0ca99483c Store command history when terminating with an error 2017-06-20 04:41:58 +02:00
Clifford Wolf 05df3dbee4 Add "setundef -anyseq" 2017-05-28 11:59:05 +02:00
Clifford Wolf 662a047815 Enable readline and tcl in mxe builds 2017-05-17 20:46:22 +02:00
Clifford Wolf 6934b862d3 Add missing AndnotGate() and OrnotGate() declarations to rtlil.h 2017-05-17 19:10:57 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf fcb274a564 Add ConstEval defaultval feature 2017-04-05 11:25:22 +02:00
Clifford Wolf b8d7f57f61 Add front-end detection for *.tcl files 2017-03-28 12:13:58 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf c6d8d70109 Fix mingw compile issue (2nd attempt) 2017-02-23 14:21:02 +01:00
Clifford Wolf 0822b21844 Fix mingw compile issue (maybe.. I can't test it) 2017-02-23 13:59:02 +01:00
Clifford Wolf e6d56d23b5 Fix eval implementation of $_NOR_ 2017-02-16 12:17:03 +01:00
Clifford Wolf 828303791b Add "yosys -w" for suppressing warnings 2017-02-12 11:11:00 +01:00
Clifford Wolf 63dfdb5d7f Add log_wire() API 2017-02-11 11:08:36 +01:00
Clifford Wolf aab58045a8 Fix undef propagation bug in $pmux SAT model 2017-02-05 22:43:33 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf b54972c112 Fix RTLIL::Memory::start_offset initialization 2017-01-25 17:00:59 +01:00
Clifford Wolf 6b2c23c721 Bugfix in RTLIL::SigSpec::remove2() 2016-12-31 16:14:42 +01:00
Clifford Wolf 33a22f8768 Simplified log_spacer() code 2016-12-23 02:06:46 +01:00
Clifford Wolf a0dff87a57 Added "yosys -W regex" 2016-12-22 23:41:44 +01:00
Clifford Wolf f144adec58 Added AIGER back-end to automatic back-end detection 2016-12-21 10:16:47 +01:00
Clifford Wolf 00761de1b7 Bugfix in comment handling 2016-12-13 13:48:09 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf fa535c0b00 Some minor build fixes for Visual C 2016-10-14 18:36:02 +02:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 59508c99b4 define PATH_MAX if not defined by limits.h 2016-10-11 12:12:09 +02:00
Clifford Wolf cb7dbf4070 Improvements in assertpmux 2016-09-07 12:42:16 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf f8a77abfac Added glob support to all front-ends 2016-08-22 15:05:57 +02:00
William D. Jones 5299b17056 Add MSYS2-compatible build. 2016-08-16 14:41:59 -04:00
Clifford Wolf 5767e4bc4d Use _Exit(0) on win32, always use _Exit(1) in log_error() 2016-08-16 09:38:54 +02:00
Clifford Wolf 39da8eddae Added log_const() API 2016-08-09 19:56:10 +02:00
Yury Gribov f7730d43bb Use /proc/self/exe on Cygwin as well. 2016-08-08 12:00:27 +02:00
Clifford Wolf 8d88fcb270 Added SatGen support for $anyconst 2016-07-27 15:52:20 +02:00
Clifford Wolf 9540be1d45 Removed $predict support from SatGen 2016-07-27 15:44:11 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf 8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf 89deb412c6 Added satgen initstate support 2016-07-22 10:28:45 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Ruben Undheim 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf ebece2b8d5 Added $sop SAT model 2016-06-17 17:47:30 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 864eeadcd9 Added missing "#define HASHLIB_H" 2016-05-14 11:43:20 +02:00
Clifford Wolf 570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf f103bfb9ba Fixes for MXE build 2016-05-07 10:53:18 +02:00
Clifford Wolf 9aa4b3309c Added "yosys -D ALL" 2016-04-24 17:12:34 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf a07f893a5f Minor hashlib bugfix 2016-04-16 23:20:11 +02:00
Clifford Wolf ace462237f Hashlib indenting fix 2016-04-05 13:25:23 +02:00
Clifford Wolf 2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Clifford Wolf 6f1b6dc322 Added log_dump() support for dict<> and pool<> containers 2016-03-31 09:57:44 +02:00
Clifford Wolf 0db53284fd We have 2016 for a while now 2016-03-30 13:52:26 +02:00
Clifford Wolf 48dbc75bed Added .vhd file extension support 2016-03-30 13:24:49 +02:00
Clifford Wolf 95784437ac Merge pull request #137 from ravenexp/master 
Embed DATDIR make variable value into yosys binary.
 2016-03-28 16:54:23 +02:00
Sebastian Kuzminsky 73870c1edf fix a cut-n-paste error in the -h help 2016-03-26 11:15:35 -06:00
Sergey Kvachonok 963c0d2525 Embed DATDIR make variable value into yosys binary. 
Use it as the last resort in the share/ directory location search.
 2016-03-26 11:16:53 +03:00
Clifford Wolf 45af4a4acf Use easyer-to-read unoptimized ceil_log2() 
see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c
 2016-02-15 23:06:18 +01:00
Clifford Wolf 0c4b311242 Fixed more visual studio warnings 2016-02-14 09:35:25 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf ba407da187 Added addBufGate module method 2016-02-02 11:26:07 +01:00
Clifford Wolf 01bcc5663f SigMap performance improvement 2016-02-01 10:10:20 +01:00
Clifford Wolf ea492abcf0 hashlib mfp<> performance improvements 2016-02-01 10:03:03 +01:00
Clifford Wolf 13e15a24a2 Added reserve() method to haslib classes and 
calculate hashtable size based on entries capacity, not size
 2016-01-31 22:50:34 +01:00
Rick Altherr 3c48de8e21 rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) 
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing.  Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits.  Using chunks for the pattern minimizes the number of
iterations in the outer loop.
 2016-01-31 09:20:16 -08:00
Rick Altherr 0265d7b100 rtlil: speed up SigSpec::sort_and_unify() 
std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup.  In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups.  Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss.  Instead, sort the vector<> that already exists and then apply
std::unique().
 2016-01-31 09:20:16 -08:00
Rick Altherr 89dc40f162 rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Rick Altherr cd3e1095b0 rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) 2016-01-31 09:20:16 -08:00
Clifford Wolf 5462399c88 Meaningless coding style change 2016-01-31 16:12:35 +01:00
Rick Altherr 43756559d8 rtlil: rewrite remove2() to avoid copying 2016-01-30 00:28:07 -08:00
Rick Altherr 12ebdef17c rtlil: duplicate remove2() for std::set<> 2016-01-29 23:06:40 -08:00
Rick Altherr 9e26147ccd rtlil: change IdString comparison operators to take references instead of copies 2016-01-29 23:06:40 -08:00
Clifford Wolf 33a5b28e25 Added default values for hashlib at() methods 2015-12-02 20:41:57 +01:00
Clifford Wolf 276101f032 Re-added SigMap::allbits() 2015-11-30 19:43:52 +01:00