mirror of https://github.com/YosysHQ/yosys.git
rtlil: duplicate remove2() for std::set<>
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9e26147ccd
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12ebdef17c
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@ -2718,6 +2718,45 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
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check();
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}
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void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other)
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{
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if (other)
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cover("kernel.rtlil.sigspec.remove_other");
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else
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cover("kernel.rtlil.sigspec.remove");
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unpack();
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if (other != NULL) {
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log_assert(width_ == other->width_);
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other->unpack();
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}
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std::vector<RTLIL::SigBit> new_bits, new_other_bits;
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new_bits.reserve(GetSize(bits_));
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if (other != NULL)
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new_other_bits.reserve(GetSize(bits_));
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for (int i = 0; i < GetSize(bits_); i++) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i]))
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continue;
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if (other != NULL)
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new_other_bits.push_back(other->bits_[i]);
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new_bits.push_back(bits_[i]);
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}
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bits_.swap(new_bits);
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width_ = GetSize(bits_);
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if (other != NULL) {
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other->bits_.swap(new_other_bits);
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other->width_ = GetSize(other->bits_);
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}
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check();
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}
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RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
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{
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pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
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@ -670,6 +670,8 @@ public:
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void remove(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other) const;
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void remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
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void remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigSpec *other);
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void remove(int offset, int length = 1);
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void remove_const();
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