Added Wrappers for:

-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h

Makefile

@@ -19,7 +19,7 @@ ENABLE_PROTOBUF := 0
 
 # python wrappers
 ENABLE_PYTHON := 1
-PYTHON_VERSION := 3.6
+PYTHON_VERSION := 3.5
 
 # other configuration flags
 ENABLE_GPROF := 0
@@ -233,7 +233,7 @@ TARGETS += libyosys.so
 endif
 
 ifeq ($(ENABLE_PYTHON),1)
-LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION))
+LDLIBS += -lpython$(PYTHON_VERSION)m -lboost_python-py$(subst .,,$(PYTHON_VERSION)) -lboost_system
 CXXFLAGS += -I/usr/include/python$(PYTHON_VERSION) -D WITH_PYTHON
 OBJS += kernel/python_wrappers.o
 endif

kernel/rtlil.cc

@@ -74,6 +74,13 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
 		this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
 }
 
+RTLIL::Const::Const(const RTLIL::Const &c)
+{
+	flags = c.flags;
+	for (auto b : c.bits)
+		this->bits.push_back(b);
+}
+
 bool RTLIL::Const::operator <(const RTLIL::Const &other) const
 {
 	if (bits.size() != other.bits.size())
@@ -2247,6 +2254,9 @@ RTLIL::Memory::Memory()
 	width = 1;
 	start_offset = 0;
 	size = 0;
+#ifdef WITH_PYTHON
+	RTLIL::Memory::get_all_memorys()->insert(std::pair<unsigned int, RTLIL::Memory*>(hashidx_, this));
+#endif
 }
 
 RTLIL::Cell::Cell() : module(nullptr)
@@ -2534,6 +2544,14 @@ RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
 	width = 1;
 }
 
+RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk) : data(sigchunk.data)
+{
+	wire = sigchunk.wire;
+	data = sigchunk.data;
+	width = sigchunk.width;
+	offset = sigchunk.offset;
+}
+
 RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
 {
 	RTLIL::SigChunk ret;
@@ -3907,6 +3925,18 @@ RTLIL::Process *RTLIL::Process::clone() const
 
 	return new_proc;
 }
+RTLIL::Memory::~Memory()
+{
+#ifdef WITH_PYTHON
+	RTLIL::Memory::get_all_memorys()->erase(hashidx_);
+#endif
+}
 
+#ifdef WITH_PYTHON
+static std::map<unsigned int, RTLIL::Memory*> *all_memorys = new std::map<unsigned int, RTLIL::Memory*>();
+std::map<unsigned int, RTLIL::Memory*> *RTLIL::Memory::get_all_memorys(void)
+{
+	return all_memorys;
+}
+#endif
 YOSYS_NAMESPACE_END
-

kernel/rtlil.h

@@ -463,6 +463,7 @@ struct RTLIL::Const
 	Const(RTLIL::State bit, int width = 1);
 	Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
 	Const(const std::vector<bool> &bits);
+	Const(const RTLIL::Const &c);
 
 	bool operator <(const RTLIL::Const &other) const;
 	bool operator ==(const RTLIL::Const &other) const;
@@ -529,6 +530,7 @@ struct RTLIL::SigChunk
 	SigChunk(int val, int width = 32);
 	SigChunk(RTLIL::State bit, int width = 1);
 	SigChunk(RTLIL::SigBit bit);
+	SigChunk(const RTLIL::SigChunk &sigchunk);
 
 	RTLIL::SigChunk extract(int offset, int length) const;
 
@@ -553,6 +555,7 @@ struct RTLIL::SigBit
 	SigBit(const RTLIL::SigChunk &chunk);
 	SigBit(const RTLIL::SigChunk &chunk, int index);
 	SigBit(const RTLIL::SigSpec &sig);
+	SigBit(const RTLIL::SigBit &sigbit);
 
 	bool operator <(const RTLIL::SigBit &other) const;
 	bool operator ==(const RTLIL::SigBit &other) const;
@@ -874,13 +877,13 @@ struct RTLIL::Design
 		}
 	}
 
-#ifdef WITH_PYTHON
-	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
-#endif
 
 	std::vector<RTLIL::Module*> selected_modules() const;
 	std::vector<RTLIL::Module*> selected_whole_modules() const;
 	std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
+#ifdef WITH_PYTHON
+	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
+#endif
 };
 
 struct RTLIL::Module : public RTLIL::AttrObject
@@ -1175,6 +1178,10 @@ struct RTLIL::Memory : public RTLIL::AttrObject
 
 	RTLIL::IdString name;
 	int width, start_offset, size;
+#ifdef WITH_PYTHON
+	~Memory();
+	static std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);
+#endif
 };
 
 struct RTLIL::Cell : public RTLIL::AttrObject
@@ -1287,6 +1294,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
 inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
+inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;}
 
 inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
 	if (wire == other.wire)