mirror of https://github.com/YosysHQ/yosys.git
Refactor driver map generation
- Implement iterators over the driver map that enumerate signals and cells within the cones of the signal
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/* -*- c++ -*-
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_ALGO_H
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#define SATGEN_ALGO_H
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include <stack>
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YOSYS_NAMESPACE_BEGIN
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struct DriverMap : public std::map<RTLIL::SigBit, std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>>> {
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RTLIL::Module *module;
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SigMap sigmap;
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using map_t = std::map<RTLIL::SigBit, std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>>>;
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struct DriverMapConeWireIterator : public std::iterator<std::input_iterator_tag, const RTLIL::SigBit *> {
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using set_iter_t = std::set<RTLIL::SigBit>::iterator;
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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std::stack<std::pair<set_iter_t, set_iter_t>> dfs;
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DriverMapConeWireIterator(DriverMap *drvmap) : DriverMapConeWireIterator(drvmap, NULL) {}
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DriverMapConeWireIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline const RTLIL::SigBit &operator*() const { return *sig; };
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inline bool operator!=(const DriverMapConeWireIterator &other) const { return sig != other.sig; }
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inline bool operator==(const DriverMapConeWireIterator &other) const { return sig == other.sig; }
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inline void operator++()
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{
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if (drvmap->count(*sig)) {
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std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> &drv = drvmap->at(*sig);
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dfs.push(std::make_pair(drv.second.begin(), drv.second.end()));
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sig = &(*dfs.top().first);
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} else {
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while (1) {
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auto &inputs_iter = dfs.top();
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inputs_iter.first++;
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if (inputs_iter.first != inputs_iter.second) {
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sig = &(*inputs_iter.first);
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return;
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} else {
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dfs.pop();
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if (dfs.empty()) {
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sig = NULL;
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return;
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}
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}
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}
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}
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}
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};
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struct DriverMapConeWireIterable {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeWireIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline DriverMapConeWireIterator begin() { return DriverMapConeWireIterator(drvmap, sig); }
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inline DriverMapConeWireIterator end() { return DriverMapConeWireIterator(drvmap); }
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};
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struct DriverMapConeCellIterator : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeWireIterator sig_iter;
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DriverMapConeCellIterator(DriverMap *drvmap) : DriverMapConeCellIterator(drvmap, NULL) {}
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DriverMapConeCellIterator(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig), sig_iter(drvmap, sig)
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{
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if ((sig != NULL) && (!drvmap->count(*sig_iter))) {
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++(*this);
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}
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}
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inline RTLIL::Cell *operator*() const
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{
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std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> &drv = drvmap->at(*sig);
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return drv.first;
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};
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inline bool operator!=(const DriverMapConeCellIterator &other) const { return sig_iter != other.sig_iter; }
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inline bool operator==(const DriverMapConeCellIterator &other) const { return sig_iter == other.sig_iter; }
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inline void operator++()
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{
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do {
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++sig_iter;
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if (sig_iter.sig == NULL) {
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return;
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}
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} while (!drvmap->count(*sig_iter));
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}
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};
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struct DriverMapConeCellIterable {
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DriverMap *drvmap;
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const RTLIL::SigBit *sig;
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DriverMapConeCellIterable(DriverMap *drvmap, const RTLIL::SigBit *sig) : drvmap(drvmap), sig(sig) {}
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inline DriverMapConeCellIterator begin() { return DriverMapConeCellIterator(drvmap, sig); }
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inline DriverMapConeCellIterator end() { return DriverMapConeCellIterator(drvmap); }
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};
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DriverMap(RTLIL::Module *module) : module(module), sigmap(module)
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &it : module->cells_) {
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if (ct.cell_known(it.second->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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for (auto &port : it.second->connections()) {
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std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
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if (ct.cell_output(it.second->type, port.first))
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outputs.insert(bits.begin(), bits.end());
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else
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inputs.insert(bits.begin(), bits.end());
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}
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std::pair<RTLIL::Cell *, std::set<RTLIL::SigBit>> drv(it.second, inputs);
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for (auto &bit : outputs)
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(*this)[bit] = drv;
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}
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}
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}
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DriverMapConeWireIterable cone(const RTLIL::SigBit &sig) { return DriverMapConeWireIterable(this, &sig); }
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DriverMapConeCellIterable cell_cone(const RTLIL::SigBit &sig) { return DriverMapConeCellIterable(this, &sig); }
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};
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YOSYS_NAMESPACE_END
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#endif
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