mirror of https://github.com/YosysHQ/yosys.git
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
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34969d4140
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@ -2584,18 +2584,26 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
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void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const
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{
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log_assert(other != NULL);
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log_assert(width_ == other->width_);
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log_assert(pattern.width_ == with.width_);
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pattern.unpack();
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with.unpack();
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unpack();
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other->unpack();
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dict<RTLIL::SigBit, RTLIL::SigBit> rules;
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for (int i = 0; i < GetSize(pattern.bits_); i++) {
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if (pattern.bits_[i].wire != NULL) {
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for (int j = 0; j < GetSize(bits_); j++) {
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if (bits_[j] == pattern.bits_[i]) {
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other->bits_[j] = with.bits_[i];
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}
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}
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}
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}
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for (int i = 0; i < GetSize(pattern.bits_); i++)
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if (pattern.bits_[i].wire != NULL)
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rules[pattern.bits_[i]] = with.bits_[i];
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replace(rules, other);
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other->check();
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}
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void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules)
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