mirror of https://github.com/YosysHQ/yosys.git
Added previousely missed functions
This commit is contained in:
Benedikt Tutzer
parent
29efc9d0b1
commit
334bfce4c4
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@ -36,7 +36,7 @@ namespace YOSYS_PYTHON {
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void log(std::string text)
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{
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Yosys::log(text.c_str());
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Yosys::log("%s",text.c_str());
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}
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struct IdString
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@ -74,11 +74,23 @@ namespace YOSYS_PYTHON {
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//WRAPPED static inline void put_reference(int idx)
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static inline void put_reference(int idx);
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//WRAPPED std::string str() const {
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std::string str();
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//WRAPPED bool empty() const {
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bool empty();
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//WRAPPED void clear() {
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void clear();
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//WRAPPED bool in(IdString rhs) const { return *this == rhs; }
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bool in_IdString(IdString *rhs);
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//WRAPPED bool in(const std::string &rhs) const { return *this == rhs; }
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bool in_std_string(std::string rhs);
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//WRAPPED bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }
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bool in_pool_IdString(boost::python::list *rhs);
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};
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std::ostream &operator<<(std::ostream &ostr, const IdString &ref)
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@ -110,12 +122,36 @@ namespace YOSYS_PYTHON {
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return ref_obj;
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}
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//WRAPPED bool as_bool() const;
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bool as_bool();
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//WRAPPED int as_int(bool is_signed = false) const;
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int as_int(bool is_signed = false);
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//WRAPPED std::string as_string() const;
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std::string as_string();
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//WRAPPED static Const from_string(std::string str);
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static Const from_string(std::string str);
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//WRAPPED std::string decode_string() const;
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std::string decode_string();
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//WRAPPED inline int size() const { return bits.size(); }
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inline int size();
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//WRAPPED bool is_fully_zero() const;
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bool is_fully_zero();
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//WRAPPED bool is_fully_ones() const;
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bool is_fully_ones();
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//WRAPPED bool is_fully_def() const;
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bool is_fully_def();
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//WRAPPED bool is_fully_undef() const;
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bool is_fully_undef();
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//WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
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inline Const extract(int offset, int len = 1, State padding = RTLIL::State::S0);
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};
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@ -148,6 +184,9 @@ namespace YOSYS_PYTHON {
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{
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return ref_obj;
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}
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//WRAPPED RTLIL::CaseRule *clone() const;
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CaseRule clone();
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};
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std::ostream &operator<<(std::ostream &ostr, const CaseRule &ref)
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@ -178,6 +217,9 @@ namespace YOSYS_PYTHON {
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{
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return ref_obj;
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}
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//WRAPPED RTLIL::SwitchRule *clone() const;
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SwitchRule clone();
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};
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std::ostream &operator<<(std::ostream &ostr, const SwitchRule &ref)
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@ -208,6 +250,9 @@ namespace YOSYS_PYTHON {
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{
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return ref_obj;
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}
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//WRAPPED RTLIL::SyncRule *clone() const;
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SyncRule clone();
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};
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std::ostream &operator<<(std::ostream &ostr, const SyncRule &ref)
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@ -238,6 +283,9 @@ namespace YOSYS_PYTHON {
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{
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return ref_obj;
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}
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//WRAPPED RTLIL::Process *clone() const;
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Process clone();
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};
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std::ostream &operator<<(std::ostream &ostr, const Process &ref)
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@ -332,6 +380,12 @@ namespace YOSYS_PYTHON {
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return ref_obj;
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}
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//WRAPPED inline int size() const { return width_; }
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inline int size();
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//WRAPPED inline bool empty() const { return width_ == 0; }
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inline bool empty();
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//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
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void replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with);
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@ -383,9 +437,57 @@ namespace YOSYS_PYTHON {
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//WRAPPED RTLIL::SigSpec repeat(int num) const;
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SigSpec repeat(int num);
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//WRAPPED bool is_wire() const;
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bool is_wire();
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//WRAPPED bool is_chunk() const;
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bool is_chunk();
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//WRAPPED inline bool is_bit() const { return width_ == 1; }
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inline bool is_bit();
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//WRAPPED bool is_fully_const() const;
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bool is_fully_const();
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//WRAPPED bool is_fully_zero() const;
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bool is_fully_zero();
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//WRAPPED bool is_fully_ones() const;
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bool is_fully_ones();
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//WRAPPED bool is_fully_def() const;
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bool is_fully_def();
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//WRAPPED bool is_fully_undef() const;
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bool is_fully_undef();
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//WRAPPED bool has_const() const;
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bool has_const();
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//WRAPPED bool has_marked_bits() const;
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bool has_marked_bits();
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//WRAPPED bool as_bool() const;
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bool as_bool();
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//WRAPPED int as_int(bool is_signed = false) const;
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int as_int(bool is_signed = false);
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//WRAPPED std::string as_string() const;
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std::string as_string();
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//WRAPPED RTLIL::Const as_const() const;
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Const as_const();
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//WRAPPED RTLIL::Wire *as_wire() const;
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Wire as_wire();
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//WRAPPED RTLIL::SigChunk as_chunk() const;
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SigChunk as_chunk();
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//WRAPPED RTLIL::SigBit as_bit() const;
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SigBit as_bit();
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//WRAPPED bool match(std::string pattern) const;
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bool match(std::string pattern);
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@ -397,6 +499,9 @@ namespace YOSYS_PYTHON {
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//WRAPPED static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
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static bool parse_rhs(SigSpec *lhs, SigSpec *sig, Module *module, std::string str);
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//WRAPPED void check() const;
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void check();
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};
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std::ostream &operator<<(std::ostream &ostr, const SigSpec &ref)
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@ -432,6 +537,9 @@ namespace YOSYS_PYTHON {
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//WRAPPED void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
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void setPort(IdString *portname, SigSpec *signal);
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//WRAPPED bool known() const;
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bool known();
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//WRAPPED bool input(RTLIL::IdString portname) const;
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bool input(IdString *portname);
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@ -449,6 +557,9 @@ namespace YOSYS_PYTHON {
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//WRAPPED void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
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void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
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//WRAPPED bool has_keep_attr() const {
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bool has_keep_attr();
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};
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std::ostream &operator<<(std::ostream &ostr, const Cell &ref)
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@ -578,6 +689,24 @@ namespace YOSYS_PYTHON {
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//WRAPPED void cloneInto(RTLIL::Module *new_mod) const;
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void cloneInto(Module *new_mod);
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//WRAPPED bool has_memories() const;
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bool has_memories();
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//WRAPPED bool has_processes() const;
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bool has_processes();
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//WRAPPED bool has_memories_warn() const;
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bool has_memories_warn();
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//WRAPPED bool has_processes_warn() const;
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bool has_processes_warn();
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//WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
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Wire wire(IdString *id);
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//WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
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Cell cell(IdString *id);
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//WRAPPED void remove(const pool<RTLIL::Wire*> &wires);
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void remove_pool_Wire(boost::python::list *wires);
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@ -1104,6 +1233,9 @@ namespace YOSYS_PYTHON {
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//WRAPPED bool selected_whole_module(RTLIL::Module *mod) const;
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bool selected_whole_module_Module(Module *mod);
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//WRAPPED bool full_selection() const {
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bool full_selection();
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};
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std::ostream &operator<<(std::ostream &ostr, const Design &ref)
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@ -1557,6 +1689,24 @@ namespace YOSYS_PYTHON {
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Yosys::RTLIL::IdString::put_reference(idx);
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}
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//WRAPPED std::string str() const {
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std::string IdString::str()
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{
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return this->get_cpp_obj()->str();
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}
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//WRAPPED bool empty() const {
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bool IdString::empty()
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{
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return this->get_cpp_obj()->empty();
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}
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//WRAPPED void clear() {
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void IdString::clear()
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{
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this->get_cpp_obj()->clear();
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}
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//WRAPPED bool in(IdString rhs) const { return *this == rhs; }
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bool IdString::in_IdString(IdString *rhs)
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{
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@ -1569,30 +1719,124 @@ namespace YOSYS_PYTHON {
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return this->get_cpp_obj()->in(rhs);
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}
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//WRAPPED bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; }
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bool IdString::in_pool_IdString(boost::python::list *rhs)
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{
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pool<Yosys::RTLIL::IdString> rhs_;
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for(int i = 0; i < len(*rhs); ++i)
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{
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}
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return this->get_cpp_obj()->in(rhs_);
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}
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//WRAPPED bool as_bool() const;
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bool Const::as_bool()
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{
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return this->get_cpp_obj()->as_bool();
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}
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//WRAPPED int as_int(bool is_signed = false) const;
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int Const::as_int(bool is_signed)
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{
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return this->get_cpp_obj()->as_int(is_signed);
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}
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//WRAPPED std::string as_string() const;
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std::string Const::as_string()
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{
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return this->get_cpp_obj()->as_string();
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}
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//WRAPPED static Const from_string(std::string str);
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Const Const::from_string(std::string str)
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{
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return Const(Yosys::RTLIL::Const::from_string(str));
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}
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//WRAPPED std::string decode_string() const;
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std::string Const::decode_string()
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{
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return this->get_cpp_obj()->decode_string();
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}
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//WRAPPED inline int size() const { return bits.size(); }
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inline int Const::size()
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{
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return this->get_cpp_obj()->size();
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}
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//WRAPPED bool is_fully_zero() const;
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bool Const::is_fully_zero()
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{
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return this->get_cpp_obj()->is_fully_zero();
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}
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//WRAPPED bool is_fully_ones() const;
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bool Const::is_fully_ones()
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{
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return this->get_cpp_obj()->is_fully_ones();
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}
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//WRAPPED bool is_fully_def() const;
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bool Const::is_fully_def()
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{
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return this->get_cpp_obj()->is_fully_def();
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}
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//WRAPPED bool is_fully_undef() const;
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bool Const::is_fully_undef()
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{
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return this->get_cpp_obj()->is_fully_undef();
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}
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//WRAPPED inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
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inline Const Const::extract(int offset, int len, State padding)
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{
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return Const(this->get_cpp_obj()->extract(offset, len, padding));
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}
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//WRAPPED RTLIL::CaseRule *clone() const;
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CaseRule CaseRule::clone()
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{
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return CaseRule(this->get_cpp_obj()->clone());
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}
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//WRAPPED RTLIL::SwitchRule *clone() const;
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SwitchRule SwitchRule::clone()
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{
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return SwitchRule(this->get_cpp_obj()->clone());
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}
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//WRAPPED RTLIL::SyncRule *clone() const;
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SyncRule SyncRule::clone()
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{
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return SyncRule(this->get_cpp_obj()->clone());
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}
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//WRAPPED RTLIL::Process *clone() const;
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Process Process::clone()
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{
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return Process(this->get_cpp_obj()->clone());
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}
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//WRAPPED RTLIL::SigChunk extract(int offset, int length) const;
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SigChunk SigChunk::extract(int offset, int length)
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{
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return SigChunk(this->get_cpp_obj()->extract(offset, length));
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}
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//WRAPPED inline int size() const { return width_; }
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inline int SigSpec::size()
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{
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return this->get_cpp_obj()->size();
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}
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//WRAPPED inline bool empty() const { return width_ == 0; }
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inline bool SigSpec::empty()
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{
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return this->get_cpp_obj()->empty();
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}
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//WRAPPED void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
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void SigSpec::replace_SigSpec_SigSpec(SigSpec *pattern, SigSpec *with)
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{
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@ -1711,12 +1955,108 @@ namespace YOSYS_PYTHON {
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return SigSpec(this->get_cpp_obj()->repeat(num));
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}
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//WRAPPED bool is_wire() const;
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bool SigSpec::is_wire()
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{
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return this->get_cpp_obj()->is_wire();
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}
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//WRAPPED bool is_chunk() const;
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bool SigSpec::is_chunk()
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{
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return this->get_cpp_obj()->is_chunk();
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}
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//WRAPPED inline bool is_bit() const { return width_ == 1; }
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inline bool SigSpec::is_bit()
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{
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return this->get_cpp_obj()->is_bit();
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}
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//WRAPPED bool is_fully_const() const;
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bool SigSpec::is_fully_const()
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{
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return this->get_cpp_obj()->is_fully_const();
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}
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//WRAPPED bool is_fully_zero() const;
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bool SigSpec::is_fully_zero()
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{
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return this->get_cpp_obj()->is_fully_zero();
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}
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//WRAPPED bool is_fully_ones() const;
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bool SigSpec::is_fully_ones()
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{
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return this->get_cpp_obj()->is_fully_ones();
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}
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//WRAPPED bool is_fully_def() const;
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bool SigSpec::is_fully_def()
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{
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return this->get_cpp_obj()->is_fully_def();
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}
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//WRAPPED bool is_fully_undef() const;
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bool SigSpec::is_fully_undef()
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{
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return this->get_cpp_obj()->is_fully_undef();
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}
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//WRAPPED bool has_const() const;
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bool SigSpec::has_const()
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{
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return this->get_cpp_obj()->has_const();
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}
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//WRAPPED bool has_marked_bits() const;
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bool SigSpec::has_marked_bits()
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{
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return this->get_cpp_obj()->has_marked_bits();
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}
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//WRAPPED bool as_bool() const;
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bool SigSpec::as_bool()
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{
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return this->get_cpp_obj()->as_bool();
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}
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//WRAPPED int as_int(bool is_signed = false) const;
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int SigSpec::as_int(bool is_signed)
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{
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return this->get_cpp_obj()->as_int(is_signed);
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}
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//WRAPPED std::string as_string() const;
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std::string SigSpec::as_string()
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{
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return this->get_cpp_obj()->as_string();
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}
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//WRAPPED RTLIL::Const as_const() const;
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Const SigSpec::as_const()
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{
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return Const(this->get_cpp_obj()->as_const());
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}
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//WRAPPED RTLIL::Wire *as_wire() const;
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Wire SigSpec::as_wire()
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{
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return Wire(this->get_cpp_obj()->as_wire());
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}
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//WRAPPED RTLIL::SigChunk as_chunk() const;
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SigChunk SigSpec::as_chunk()
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{
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return SigChunk(this->get_cpp_obj()->as_chunk());
|
||||
}
|
||||
|
||||
//WRAPPED RTLIL::SigBit as_bit() const;
|
||||
SigBit SigSpec::as_bit()
|
||||
{
|
||||
return SigBit(this->get_cpp_obj()->as_bit());
|
||||
}
|
||||
|
||||
//WRAPPED bool match(std::string pattern) const;
|
||||
bool SigSpec::match(std::string pattern)
|
||||
{
|
||||
|
|
@ -1741,6 +2081,12 @@ namespace YOSYS_PYTHON {
|
|||
return Yosys::RTLIL::SigSpec::parse_rhs(*lhs->get_cpp_obj(), *sig->get_cpp_obj(), module->get_cpp_obj(), str);
|
||||
}
|
||||
|
||||
//WRAPPED void check() const;
|
||||
void SigSpec::check()
|
||||
{
|
||||
this->get_cpp_obj()->check();
|
||||
}
|
||||
|
||||
//WRAPPED bool hasPort(RTLIL::IdString portname) const;
|
||||
bool Cell::hasPort(IdString *portname)
|
||||
{
|
||||
|
|
@ -1759,6 +2105,12 @@ namespace YOSYS_PYTHON {
|
|||
this->get_cpp_obj()->setPort(*portname->get_cpp_obj(), *signal->get_cpp_obj());
|
||||
}
|
||||
|
||||
//WRAPPED bool known() const;
|
||||
bool Cell::known()
|
||||
{
|
||||
return this->get_cpp_obj()->known();
|
||||
}
|
||||
|
||||
//WRAPPED bool input(RTLIL::IdString portname) const;
|
||||
bool Cell::input(IdString *portname)
|
||||
{
|
||||
|
|
@ -1795,6 +2147,12 @@ namespace YOSYS_PYTHON {
|
|||
this->get_cpp_obj()->fixup_parameters(set_a_signed, set_b_signed);
|
||||
}
|
||||
|
||||
//WRAPPED bool has_keep_attr() const {
|
||||
bool Cell::has_keep_attr()
|
||||
{
|
||||
return this->get_cpp_obj()->has_keep_attr();
|
||||
}
|
||||
|
||||
//WRAPPED void connect(const RTLIL::SigSig &conn);
|
||||
void Module::connect_SigSig(PyObject* conn)
|
||||
{
|
||||
|
|
@ -1828,6 +2186,42 @@ namespace YOSYS_PYTHON {
|
|||
this->get_cpp_obj()->cloneInto(new_mod->get_cpp_obj());
|
||||
}
|
||||
|
||||
//WRAPPED bool has_memories() const;
|
||||
bool Module::has_memories()
|
||||
{
|
||||
return this->get_cpp_obj()->has_memories();
|
||||
}
|
||||
|
||||
//WRAPPED bool has_processes() const;
|
||||
bool Module::has_processes()
|
||||
{
|
||||
return this->get_cpp_obj()->has_processes();
|
||||
}
|
||||
|
||||
//WRAPPED bool has_memories_warn() const;
|
||||
bool Module::has_memories_warn()
|
||||
{
|
||||
return this->get_cpp_obj()->has_memories_warn();
|
||||
}
|
||||
|
||||
//WRAPPED bool has_processes_warn() const;
|
||||
bool Module::has_processes_warn()
|
||||
{
|
||||
return this->get_cpp_obj()->has_processes_warn();
|
||||
}
|
||||
|
||||
//WRAPPED RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
|
||||
Wire Module::wire(IdString *id)
|
||||
{
|
||||
return Wire(this->get_cpp_obj()->wire(*id->get_cpp_obj()));
|
||||
}
|
||||
|
||||
//WRAPPED RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
|
||||
Cell Module::cell(IdString *id)
|
||||
{
|
||||
return Cell(this->get_cpp_obj()->cell(*id->get_cpp_obj()));
|
||||
}
|
||||
|
||||
//WRAPPED void remove(const pool<RTLIL::Wire*> &wires);
|
||||
void Module::remove_pool_Wire(boost::python::list *wires)
|
||||
{
|
||||
|
|
@ -2780,6 +3174,12 @@ namespace YOSYS_PYTHON {
|
|||
return this->get_cpp_obj()->selected_whole_module(mod->get_cpp_obj());
|
||||
}
|
||||
|
||||
//WRAPPED bool full_selection() const {
|
||||
bool Design::full_selection()
|
||||
{
|
||||
return this->get_cpp_obj()->full_selection();
|
||||
}
|
||||
|
||||
struct Initializer
|
||||
{
|
||||
Initializer() {
|
||||
|
|
@ -2853,36 +3253,52 @@ namespace YOSYS_PYTHON {
|
|||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("get_reference", &IdString::get_reference)
|
||||
.def("put_reference", &IdString::put_reference)
|
||||
.def("str", &IdString::str)
|
||||
.def("empty", &IdString::empty)
|
||||
.def("clear", &IdString::clear)
|
||||
.def("in_IdString", &IdString::in_IdString)
|
||||
.def("in_std_string", &IdString::in_std_string)
|
||||
.def("in_pool_IdString", &IdString::in_pool_IdString)
|
||||
;
|
||||
|
||||
class_<Const>("Const")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("as_bool", &Const::as_bool)
|
||||
.def("as_int", &Const::as_int)
|
||||
.def("as_string", &Const::as_string)
|
||||
.def("from_string", &Const::from_string)
|
||||
.def("decode_string", &Const::decode_string)
|
||||
.def("size", &Const::size)
|
||||
.def("is_fully_zero", &Const::is_fully_zero)
|
||||
.def("is_fully_ones", &Const::is_fully_ones)
|
||||
.def("is_fully_def", &Const::is_fully_def)
|
||||
.def("is_fully_undef", &Const::is_fully_undef)
|
||||
.def("extract", &Const::extract)
|
||||
;
|
||||
|
||||
class_<CaseRule>("CaseRule")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("clone", &CaseRule::clone)
|
||||
;
|
||||
|
||||
class_<SwitchRule>("SwitchRule")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("clone", &SwitchRule::clone)
|
||||
;
|
||||
|
||||
class_<SyncRule>("SyncRule")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("clone", &SyncRule::clone)
|
||||
;
|
||||
|
||||
class_<Process>("Process")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("clone", &Process::clone)
|
||||
;
|
||||
|
||||
class_<SigChunk>("SigChunk")
|
||||
|
|
@ -2899,6 +3315,8 @@ namespace YOSYS_PYTHON {
|
|||
class_<SigSpec>("SigSpec")
|
||||
.def(boost::python::self_ns::str(boost::python::self_ns::self))
|
||||
.def(boost::python::self_ns::repr(boost::python::self_ns::self))
|
||||
.def("size", &SigSpec::size)
|
||||
.def("empty", &SigSpec::empty)
|
||||
.def("replace_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec)
|
||||
.def("replace_SigSpec_SigSpec_SigSpec", &SigSpec::replace_SigSpec_SigSpec_SigSpec)
|
||||
.def("replace_int_SigSpec", &SigSpec::replace_int_SigSpec)
|
||||
|
|
@ -2916,11 +3334,28 @@ namespace YOSYS_PYTHON {
|
|||
.def("append_bit", &SigSpec::append_bit)
|
||||
.def("extend_u0", &SigSpec::extend_u0)
|
||||
.def("repeat", &SigSpec::repeat)
|
||||
.def("is_wire", &SigSpec::is_wire)
|
||||
.def("is_chunk", &SigSpec::is_chunk)
|
||||
.def("is_bit", &SigSpec::is_bit)
|
||||
.def("is_fully_const", &SigSpec::is_fully_const)
|
||||
.def("is_fully_zero", &SigSpec::is_fully_zero)
|
||||
.def("is_fully_ones", &SigSpec::is_fully_ones)
|
||||
.def("is_fully_def", &SigSpec::is_fully_def)
|
||||
.def("is_fully_undef", &SigSpec::is_fully_undef)
|
||||
.def("has_const", &SigSpec::has_const)
|
||||
.def("has_marked_bits", &SigSpec::has_marked_bits)
|
||||
.def("as_bool", &SigSpec::as_bool)
|
||||
.def("as_int", &SigSpec::as_int)
|
||||
.def("as_string", &SigSpec::as_string)
|
||||
.def("as_const", &SigSpec::as_const)
|
||||
.def("as_wire", &SigSpec::as_wire)
|
||||
.def("as_chunk", &SigSpec::as_chunk)
|
||||
.def("as_bit", &SigSpec::as_bit)
|
||||
.def("match", &SigSpec::match)
|
||||
.def("parse", &SigSpec::parse)
|
||||
.def("parse_sel", &SigSpec::parse_sel)
|
||||
.def("parse_rhs", &SigSpec::parse_rhs)
|
||||
.def("check", &SigSpec::check)
|
||||
;
|
||||
|
||||
class_<Cell>("Cell", no_init)
|
||||
|
|
@ -2929,12 +3364,14 @@ namespace YOSYS_PYTHON {
|
|||
.def("hasPort", &Cell::hasPort)
|
||||
.def("unsetPort", &Cell::unsetPort)
|
||||
.def("setPort", &Cell::setPort)
|
||||
.def("known", &Cell::known)
|
||||
.def("input", &Cell::input)
|
||||
.def("output", &Cell::output)
|
||||
.def("hasParam", &Cell::hasParam)
|
||||
.def("unsetParam", &Cell::unsetParam)
|
||||
.def("setParam", &Cell::setParam)
|
||||
.def("fixup_parameters", &Cell::fixup_parameters)
|
||||
.def("has_keep_attr", &Cell::has_keep_attr)
|
||||
;
|
||||
|
||||
class_<Wire>("Wire", no_init)
|
||||
|
|
@ -2957,6 +3394,12 @@ namespace YOSYS_PYTHON {
|
|||
.def("connect_SigSpec_SigSpec", &Module::connect_SigSpec_SigSpec)
|
||||
.def("new_connections", &Module::new_connections)
|
||||
.def("cloneInto", &Module::cloneInto)
|
||||
.def("has_memories", &Module::has_memories)
|
||||
.def("has_processes", &Module::has_processes)
|
||||
.def("has_memories_warn", &Module::has_memories_warn)
|
||||
.def("has_processes_warn", &Module::has_processes_warn)
|
||||
.def("wire", &Module::wire)
|
||||
.def("cell", &Module::cell)
|
||||
.def("remove_pool_Wire", &Module::remove_pool_Wire)
|
||||
.def("remove_Cell", &Module::remove_Cell)
|
||||
.def("rename_Wire_IdString", &Module::rename_Wire_IdString)
|
||||
|
|
@ -3123,6 +3566,7 @@ namespace YOSYS_PYTHON {
|
|||
.def("selected_member", &Design::selected_member)
|
||||
.def("selected_module_Module", &Design::selected_module_Module)
|
||||
.def("selected_whole_module_Module", &Design::selected_whole_module_Module)
|
||||
.def("full_selection", &Design::full_selection)
|
||||
;
|
||||
|
||||
def("escape_id", escape_id);
|
||||
|
|
|
|||
Loading…
Reference in New Issue