mirror of https://github.com/YosysHQ/yosys.git
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -47,16 +47,20 @@ struct IlangFrontend : public Frontend {
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log(" -nooverwrite\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message if the existing module is not a blackbox\n");
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log(" module, and overwrite the existing module if it is a blackbox module.)\n");
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log(" module, and overwrite the existing module if it is a blackbox module.)\n");
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log("\n");
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log(" -overwrite\n");
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log(" overwrite existing modules with the same name\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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ILANG_FRONTEND::flag_nooverwrite = false;
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ILANG_FRONTEND::flag_overwrite = false;
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ILANG_FRONTEND::flag_lib = false;
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log_header(design, "Executing ILANG frontend.\n");
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@ -73,6 +77,10 @@ struct IlangFrontend : public Frontend {
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ILANG_FRONTEND::flag_overwrite = true;
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continue;
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}
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if (arg == "-lib") {
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ILANG_FRONTEND::flag_lib = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -34,6 +34,7 @@ namespace ILANG_FRONTEND {
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extern RTLIL::Design *current_design;
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extern bool flag_nooverwrite;
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extern bool flag_overwrite;
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extern bool flag_lib;
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}
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YOSYS_NAMESPACE_END
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@ -37,7 +37,7 @@ namespace ILANG_FRONTEND {
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std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
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std::vector<RTLIL::CaseRule*> case_stack;
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dict<RTLIL::IdString, RTLIL::Const> attrbuf;
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bool flag_nooverwrite, flag_overwrite;
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bool flag_nooverwrite, flag_overwrite, flag_lib;
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bool delete_current_module;
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}
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using namespace ILANG_FRONTEND;
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@ -98,7 +98,7 @@ module:
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delete_current_module = false;
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if (current_design->has($2)) {
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RTLIL::Module *existing_mod = current_design->module($2);
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if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) {
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if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
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log("Ignoring blackbox re-definition of module %s.\n", $2);
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delete_current_module = true;
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} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
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@ -124,6 +124,8 @@ module:
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current_module->fixup_ports();
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if (delete_current_module)
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delete current_module;
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else if (flag_lib)
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current_module->makeblackbox();
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current_module = nullptr;
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} EOL;
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@ -641,6 +641,30 @@ RTLIL::Module::~Module()
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delete it->second;
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}
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void RTLIL::Module::makeblackbox()
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{
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pool<RTLIL::Wire*> delwires;
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for (auto it = wires_.begin(); it != wires_.end(); ++it)
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if (!it->second->port_input && !it->second->port_output)
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delwires.insert(it->second);
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for (auto it = memories.begin(); it != memories.end(); ++it)
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delete it->second;
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memories.clear();
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for (auto it = cells_.begin(); it != cells_.end(); ++it)
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delete it->second;
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cells_.clear();
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for (auto it = processes.begin(); it != processes.end(); ++it)
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delete it->second;
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processes.clear();
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remove(delwires);
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set_bool_attribute("\\blackbox");
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}
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void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
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{
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log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
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@ -976,6 +976,7 @@ public:
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virtual void sort();
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virtual void check();
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virtual void optimize();
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virtual void makeblackbox();
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void connect(const RTLIL::SigSig &conn);
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void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
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