mirror of https://github.com/YosysHQ/yosys.git
kernel: SigSpec copies to not trigger pack()
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4555b5b819
commit
940640ac44
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@ -2709,10 +2709,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
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RTLIL::SigChunk::SigChunk(const RTLIL::SigChunk &sigchunk)
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{
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wire = sigchunk.wire;
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data = sigchunk.data;
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width = sigchunk.width;
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offset = sigchunk.offset;
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*this = sigchunk;
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}
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RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
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@ -2785,40 +2782,14 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
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append(*it--);
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}
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const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
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RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
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{
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cover("kernel.rtlil.sigspec.assign");
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width_ = other.width_;
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hash_ = other.hash_;
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chunks_ = other.chunks_;
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bits_.clear();
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if (!other.bits_.empty())
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{
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RTLIL::SigChunk *last = NULL;
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int last_end_offset = 0;
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for (auto &bit : other.bits_) {
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if (last && bit.wire == last->wire) {
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if (bit.wire == NULL) {
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last->data.push_back(bit.data);
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last->width++;
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continue;
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} else if (last_end_offset == bit.offset) {
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last_end_offset++;
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last->width++;
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continue;
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}
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}
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chunks_.push_back(bit);
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last = &chunks_.back();
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last_end_offset = bit.offset + 1;
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}
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check();
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}
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bits_ = other.bits_;
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return *this;
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}
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@ -3009,7 +2980,7 @@ void RTLIL::SigSpec::unpack() const
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that->bits_.reserve(that->width_);
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for (auto &c : that->chunks_)
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for (int i = 0; i < c.width; i++)
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that->bits_.push_back(RTLIL::SigBit(c, i));
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that->bits_.emplace_back(c, i);
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that->chunks_.clear();
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that->hash_ = 0;
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@ -766,7 +766,7 @@ public:
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SigSpec();
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SigSpec(const RTLIL::SigSpec &other);
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SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
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const RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other);
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RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other);
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SigSpec(const RTLIL::Const &value);
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SigSpec(const RTLIL::SigChunk &chunk);
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