mirror of https://github.com/YosysHQ/yosys.git
Added satgen initstate support
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7fef5ff104
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89deb412c6
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@ -71,6 +71,7 @@ struct SatGen
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std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en;
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std::map<std::string, RTLIL::SigSpec> predict_a, predict_en;
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std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals;
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std::map<std::pair<std::string, int>, bool> initstates;
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bool ignore_div_by_zero;
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bool model_undef;
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@ -267,6 +268,13 @@ struct SatGen
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ez->assume(ez->OR(undef, ez->IFF(y, yy)));
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}
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void setInitState(int timestep)
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{
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auto key = make_pair(prefix, timestep);
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log_assert(initstates.count(key) == 0 || initstates.at(key) == true);
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initstates[key] = true;
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}
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bool importCell(RTLIL::Cell *cell, int timestep = -1)
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{
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bool arith_undef_handled = false;
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@ -1331,6 +1339,25 @@ struct SatGen
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return true;
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}
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if (cell->type == "$initstate")
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{
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auto key = make_pair(prefix, timestep);
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if (initstates.count(key) == 0)
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initstates[key] = false;
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std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
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log_assert(GetSize(y) == 1);
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ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE);
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if (model_undef) {
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
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log_assert(GetSize(undef_y) == 1);
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ez->SET(undef_y[0], ez->CONST_FALSE);
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}
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return true;
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}
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if (cell->type == "$assert")
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{
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std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
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