mirror of https://github.com/YosysHQ/yosys.git
Move ConstEvalAig to aigerparse.cc
This commit is contained in:
Eddie Hung
parent
75d89e56cf
commit
d09d4e0706
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@ -35,6 +35,162 @@
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YOSYS_NAMESPACE_BEGIN
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struct ConstEvalAig
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{
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RTLIL::Module *module;
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dict<RTLIL::SigBit, RTLIL::Const> values_map;
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SigSet<RTLIL::Cell*> sig2driver;
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dict<SigBit, pool<RTLIL::SigBit>> sig2deps;
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ConstEvalAig(RTLIL::Module *module) : module(module)
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &it : module->cells_) {
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if (!ct.cell_known(it.second->type))
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continue;
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for (auto &it2 : it.second->connections())
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if (ct.cell_output(it.second->type, it2.first))
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sig2driver.insert(it2.second, it.second);
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}
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}
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void clear()
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{
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values_map.clear();
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sig2deps.clear();
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}
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void set(RTLIL::SigSpec sig, RTLIL::Const value)
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{
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#ifndef NDEBUG
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auto it = values_map.find(sig);
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RTLIL::SigSpec current_val;
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if (it != values_map.end())
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current_val = it->second;
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for (int i = 0; i < GetSize(current_val); i++)
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log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
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#endif
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for (int i = 0; i < GetSize(sig); i++)
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values_map[sig[i]] = value[i];
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}
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void set_incremental(RTLIL::SigSpec sig, RTLIL::Const value)
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{
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log_assert(GetSize(sig) == GetSize(value));
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for (int i = 0; i < GetSize(sig); i++) {
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auto it = values_map.find(sig[i]);
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if (it != values_map.end()) {
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RTLIL::SigSpec current_val = it->second;
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if (current_val != value[i])
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for (auto dep : sig2deps[sig[i]])
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values_map.erase(dep);
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it->second = value[i];
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}
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else
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values_map[sig[i]] = value[i];
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}
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}
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void compute_deps(RTLIL::SigBit output, const pool<RTLIL::SigBit> &inputs)
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{
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sig2deps[output].insert(output);
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std::set<RTLIL::Cell*> driver_cells;
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sig2driver.find(output, driver_cells);
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for (auto cell : driver_cells) {
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_a))
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compute_deps(sig_a, inputs);
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_b))
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compute_deps(sig_b, inputs);
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}
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else if (cell->type == "$_NOT_") {
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}
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else log_abort();
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}
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}
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bool eval(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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auto it = values_map.find(sig_y);
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if (it != values_map.end())
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sig_y = it->second;
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if (sig_y.is_fully_const())
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return true;
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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if (sig_a.size() > 0 && !eval(sig_a))
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return false;
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RTLIL::Const eval_ret;
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if (cell->type == "$_NOT_") {
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if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
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else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
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}
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else if (cell->type == "$_AND_") {
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if (sig_a == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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{
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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if (sig_b.size() > 0 && !eval(sig_b))
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return false;
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if (sig_b == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) {
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eval_ret = RTLIL::State::Sx;
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goto eval_end;
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}
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eval_ret = RTLIL::State::S1;
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}
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}
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else log_abort();
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eval_end:
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set(sig_y, eval_ret);
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return true;
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}
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bool eval(RTLIL::SigSpec &sig)
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{
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auto it = values_map.find(sig);
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if (it != values_map.end())
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sig = it->second;
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if (sig.is_fully_const())
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return true;
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std::set<RTLIL::Cell*> driver_cells;
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sig2driver.find(sig, driver_cells);
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for (auto cell : driver_cells)
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if (!eval(cell))
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return false;
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it = values_map.find(sig);
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if (it != values_map.end())
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sig = it->second;
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if (sig.is_fully_const())
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return true;
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return false;
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}
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};
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
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: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
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{
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@ -249,13 +405,15 @@ void AigerReader::parse_xaiger()
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log_assert(wire);
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input_sig.append(wire);
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}
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
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for (int j = 0; j < (1 << cutLeavesM); ++j) {
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ce.clear();
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ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});
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int gray = j ^ (j >> 1);
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ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
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RTLIL::SigSpec o(output_sig);
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ce.eval(o);
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lut_mask[j] = o.as_const()[0];
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lut_mask[gray] = o.as_const()[0];
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}
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RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
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log_assert(output_cell);
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@ -390,163 +390,6 @@ struct ConstEval
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}
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};
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struct ConstEvalAig
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{
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RTLIL::Module *module;
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//SigMap assign_map;
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SigMap values_map;
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//SigPool stop_signals;
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SigSet<RTLIL::Cell*> sig2driver;
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//std::set<RTLIL::Cell*> busy;
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//std::vector<SigMap> stack;
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//RTLIL::State defaultval;
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ConstEvalAig(RTLIL::Module *module /*, RTLIL::State defaultval = RTLIL::State::Sm*/) : module(module) /*, assign_map(module), defaultval(defaultval)*/
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &it : module->cells_) {
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if (!ct.cell_known(it.second->type))
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continue;
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for (auto &it2 : it.second->connections())
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if (ct.cell_output(it.second->type, it2.first))
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sig2driver.insert(/*assign_map*/(it2.second), it.second);
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}
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}
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void clear()
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{
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values_map.clear();
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//stop_signals.clear();
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}
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//void push()
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//{
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// stack.push_back(values_map);
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//}
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//void pop()
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//{
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// values_map.swap(stack.back());
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// stack.pop_back();
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//}
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void set(RTLIL::SigSpec sig, RTLIL::Const value)
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{
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//assign_map.apply(sig);
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#ifndef NDEBUG
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RTLIL::SigSpec current_val = values_map(sig);
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for (int i = 0; i < GetSize(current_val); i++)
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log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
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#endif
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values_map.add(sig, RTLIL::SigSpec(value));
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}
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//void stop(RTLIL::SigSpec sig)
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//{
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// assign_map.apply(sig);
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// stop_signals.add(sig);
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//}
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bool eval(RTLIL::Cell *cell /*, RTLIL::SigSpec &undef*/)
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{
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RTLIL::SigSpec sig_y = values_map(/*assign_map*/(cell->getPort("\\Y")));
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if (sig_y.is_fully_const())
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return true;
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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if (sig_a.size() > 0 && !eval(sig_a /*, undef, cell*/))
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return false;
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RTLIL::Const eval_ret;
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if (cell->type == "$_NOT_") {
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if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
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else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
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}
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else if (cell->type == "$_AND_") {
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if (sig_a == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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{
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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if (sig_b.size() > 0 && !eval(sig_b /*, undef, cell*/))
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return false;
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if (sig_b == RTLIL::S0) {
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eval_ret = RTLIL::S0;
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goto eval_end;
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}
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if (sig_a != RTLIL::State::S1 || sig_b != RTLIL::State::S1) {
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eval_ret = RTLIL::State::Sx;
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goto eval_end;
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}
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eval_ret = RTLIL::State::S1;
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}
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}
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else log_abort();
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eval_end:
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set(sig_y, eval_ret);
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return true;
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}
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bool eval(RTLIL::SigSpec &sig /*, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL*/)
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{
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//assign_map.apply(sig);
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values_map.apply(sig);
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if (sig.is_fully_const())
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return true;
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//if (stop_signals.check_any(sig)) {
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// undef = stop_signals.extract(sig);
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// return false;
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//}
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//if (busy_cell) {
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// if (busy.count(busy_cell) > 0) {
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// undef = sig;
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// return false;
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// }
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// busy.insert(busy_cell);
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//}
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std::set<RTLIL::Cell*> driver_cells;
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sig2driver.find(sig, driver_cells);
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for (auto cell : driver_cells) {
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if (!eval(cell /*, undef*/)) {
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//if (busy_cell)
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// busy.erase(busy_cell);
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return false;
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}
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}
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//if (busy_cell)
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// busy.erase(busy_cell);
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values_map.apply(sig);
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if (sig.is_fully_const())
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return true;
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//for (auto &c : sig.chunks())
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// if (c.wire != NULL)
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// undef.append(c);
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return false;
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}
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//bool eval(RTLIL::SigSpec &sig)
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//{
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// RTLIL::SigSpec undef;
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// return eval(sig, undef);
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//}
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};
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YOSYS_NAMESPACE_END
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#endif
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