mirror of https://github.com/YosysHQ/yosys.git
Avoid work in replace() if rules empty.
This speeds up processing when number of bits are large but there is actually nothing to replace. Adresses part of #1382. Signed-off-by: Henner Zeller <h.zeller@acm.org>
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@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
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log_assert(other != NULL);
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log_assert(width_ == other->width_);
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if (rules.empty()) return;
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unpack();
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other->unpack();
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@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
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log_assert(other != NULL);
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log_assert(width_ == other->width_);
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if (rules.empty()) return;
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unpack();
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other->unpack();
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