mirror of https://github.com/YosysHQ/yosys.git
Pass SigBit by value to Netlist algorithms
This commit is contained in:
Bogdan Vukobratovic
parent
d69989b8d2
commit
4912567cbf
133
kernel/algo.h
133
kernel/algo.h
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@ -74,25 +74,43 @@ struct Netlist {
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namespace detail
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{
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struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const RTLIL::SigBit *> {
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struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, RTLIL::SigBit> {
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using set_iter_t = std::set<RTLIL::SigBit>::iterator;
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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RTLIL::SigBit sig;
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bool sentinel;
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std::stack<std::pair<set_iter_t, set_iter_t>> dfs_path_stack;
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std::set<RTLIL::Cell *> cells_visited;
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NetlistConeWireIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig) {}
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NetlistConeWireIter(const Netlist &net) : net(net), sentinel(true) {}
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const RTLIL::SigBit &operator*() const { return *p_sig; };
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bool operator!=(const NetlistConeWireIter &other) const { return p_sig != other.p_sig; }
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bool operator==(const NetlistConeWireIter &other) const { return p_sig == other.p_sig; }
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NetlistConeWireIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig), sentinel(false) {}
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const RTLIL::SigBit &operator*() const { return sig; };
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bool operator!=(const NetlistConeWireIter &other) const
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{
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if (sentinel || other.sentinel) {
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return sentinel != other.sentinel;
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} else {
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return sig != other.sig;
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}
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}
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bool operator==(const NetlistConeWireIter &other) const {
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if (sentinel || other.sentinel) {
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return sentinel == other.sentinel;
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} else {
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return sig == other.sig;
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}
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}
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void next_sig_in_dag()
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{
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while (1) {
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if (dfs_path_stack.empty()) {
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p_sig = NULL;
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sentinel = true;
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return;
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}
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@ -101,7 +119,7 @@ struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const
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cell_inputs_iter++;
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if (cell_inputs_iter != cell_inputs_iter_guard) {
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p_sig = &(*cell_inputs_iter);
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sig = *cell_inputs_iter;
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return;
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} else {
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dfs_path_stack.pop();
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@ -111,14 +129,14 @@ struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const
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NetlistConeWireIter &operator++()
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{
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if (net.sigbit_driver_map.count(*p_sig)) {
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auto drv = net.sigbit_driver_map.at(*p_sig);
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if (net.sigbit_driver_map.count(sig)) {
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auto drv = net.sigbit_driver_map.at(sig);
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if (!cells_visited.count(drv)) {
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auto &inputs = net.cell_inputs_map.at(drv);
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dfs_path_stack.push(std::make_pair(inputs.begin(), inputs.end()));
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cells_visited.insert(drv);
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p_sig = &(*dfs_path_stack.top().first);
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sig = (*dfs_path_stack.top().first);
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} else {
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next_sig_in_dag();
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}
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@ -131,23 +149,24 @@ struct NetlistConeWireIter : public std::iterator<std::input_iterator_tag, const
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struct NetlistConeWireIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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RTLIL::SigBit sig;
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NetlistConeWireIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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NetlistConeWireIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
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NetlistConeWireIter begin() { return NetlistConeWireIter(net, p_sig); }
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NetlistConeWireIter begin() { return NetlistConeWireIter(net, sig); }
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NetlistConeWireIter end() { return NetlistConeWireIter(net); }
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};
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struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, RTLIL::Cell *> {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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NetlistConeWireIter sig_iter;
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NetlistConeCellIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
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NetlistConeCellIter(const Netlist &net) : net(net), sig_iter(net) {}
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NetlistConeCellIter(const Netlist &net, RTLIL::SigBit sig) : net(net), sig_iter(net, sig)
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{
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if ((p_sig != NULL) && (!has_driver_cell(*sig_iter))) {
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if ((!sig_iter.sentinel) && (!has_driver_cell(*sig_iter))) {
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++(*this);
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}
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}
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@ -162,7 +181,7 @@ struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, const
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{
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while (true) {
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++sig_iter;
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if (sig_iter.p_sig == NULL) {
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if (sig_iter.sentinel) {
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return *this;
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}
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@ -179,60 +198,60 @@ struct NetlistConeCellIter : public std::iterator<std::input_iterator_tag, const
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struct NetlistConeCellIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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RTLIL::SigBit sig;
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NetlistConeCellIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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NetlistConeCellIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
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NetlistConeCellIter begin() { return NetlistConeCellIter(net, p_sig); }
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NetlistConeCellIter begin() { return NetlistConeCellIter(net, sig); }
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NetlistConeCellIter end() { return NetlistConeCellIter(net); }
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};
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struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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// struct NetlistConeInputsIter : public std::iterator<std::input_iterator_tag, const RTLIL::Cell *> {
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// const Netlist &net;
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// RTLIL::SigBit sig;
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NetlistConeWireIter sig_iter;
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// NetlistConeWireIter sig_iter;
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bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
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// bool has_driver_cell(const RTLIL::SigBit &s) { return net.sigbit_driver_map.count(s); }
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NetlistConeInputsIter(const Netlist &net, const RTLIL::SigBit *p_sig = NULL) : net(net), p_sig(p_sig), sig_iter(net, p_sig)
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{
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if ((p_sig != NULL) && (has_driver_cell(*sig_iter))) {
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++(*this);
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}
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}
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// NetlistConeInputsIter(const Netlist &net, RTLIL::SigBit sig = NULL) : net(net), sig(sig), sig_iter(net, sig)
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// {
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// if ((sig != NULL) && (has_driver_cell(sig_iter))) {
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// ++(*this);
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// }
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// }
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const RTLIL::SigBit &operator*() const { return *sig_iter; };
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bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
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bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
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NetlistConeInputsIter &operator++()
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{
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do {
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++sig_iter;
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if (sig_iter.p_sig == NULL) {
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return *this;
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}
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} while (has_driver_cell(*sig_iter));
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// const RTLIL::SigBit &operator*() const { return sig_iter; };
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// bool operator!=(const NetlistConeInputsIter &other) const { return sig_iter != other.sig_iter; }
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// bool operator==(const NetlistConeInputsIter &other) const { return sig_iter == other.sig_iter; }
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// NetlistConeInputsIter &operator++()
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// {
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// do {
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// ++sig_iter;
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// if (sig_iter->empty()) {
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// return *this;
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// }
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// } while (has_driver_cell(sig_iter));
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return *this;
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}
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};
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// return *this;
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// }
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// };
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struct NetlistConeInputsIterable {
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const Netlist &net;
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const RTLIL::SigBit *p_sig;
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// struct NetlistConeInputsIterable {
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// const Netlist &net;
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// RTLIL::SigBit sig;
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NetlistConeInputsIterable(const Netlist &net, const RTLIL::SigBit *p_sig) : net(net), p_sig(p_sig) {}
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// NetlistConeInputsIterable(const Netlist &net, RTLIL::SigBit sig) : net(net), sig(sig) {}
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NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, p_sig); }
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NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
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};
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// NetlistConeInputsIter begin() { return NetlistConeInputsIter(net, sig); }
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// NetlistConeInputsIter end() { return NetlistConeInputsIter(net); }
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// };
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} // namespace detail
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detail::NetlistConeWireIterable cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeWireIterable(net, &sig); }
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detail::NetlistConeWireIterable cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeWireIterable(net, net.sigmap(sig)); }
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// detail::NetlistConeInputsIterable cone_inputs(const RTLIL::SigBit &sig) { return NetlistConeInputsIterable(this, &sig); }
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detail::NetlistConeCellIterable cell_cone(const Netlist &net, const RTLIL::SigBit &sig) { return detail::NetlistConeCellIterable(net, &sig); }
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// detail::NetlistConeInputsIterable cone_inputs(RTLIL::SigBit sig) { return NetlistConeInputsIterable(this, &sig); }
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detail::NetlistConeCellIterable cell_cone(const Netlist &net, RTLIL::SigBit sig) { return detail::NetlistConeCellIterable(net, net.sigmap(sig)); }
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YOSYS_NAMESPACE_END
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