mirror of https://github.com/YosysHQ/yosys.git
added destructors for wires and cells
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55df7fff19
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e7d3f3cd46
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@ -2223,6 +2223,13 @@ RTLIL::Wire::Wire()
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#endif
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}
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RTLIL::Wire::~Wire()
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{
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#ifdef WITH_PYTHON
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RTLIL::Wire::get_all_wires()->erase(hashidx_);
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#endif
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}
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#ifdef WITH_PYTHON
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static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>();
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std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
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@ -2256,6 +2263,13 @@ RTLIL::Cell::Cell() : module(nullptr)
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#endif
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}
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RTLIL::Cell::~Cell()
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{
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#ifdef WITH_PYTHON
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RTLIL::Cell::get_all_cells()->erase(hashidx_);
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#endif
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}
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#ifdef WITH_PYTHON
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static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>();
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std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
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@ -1149,7 +1149,7 @@ protected:
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// use module->addWire() and module->remove() to create or destroy wires
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friend struct RTLIL::Module;
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Wire();
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~Wire() { };
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~Wire();
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public:
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// do not simply copy wires
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@ -1186,6 +1186,7 @@ protected:
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// use module->addCell() and module->remove() to create or destroy cells
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friend struct RTLIL::Module;
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Cell();
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~Cell();
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public:
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// do not simply copy cells
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