mirror of https://github.com/YosysHQ/yosys.git
removed debug output
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da8083dbd0
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55df7fff19
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@ -642,7 +642,6 @@ RTLIL::Module::Module()
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refcount_cells_ = 0;
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#ifdef WITH_PYTHON
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std::cout << "inserting module with name " << this->name.c_str() << "\n";
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RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
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#endif
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}
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