mirror of https://github.com/YosysHQ/yosys.git
Fix mingw compile issue (maybe.. I can't test it)
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34d4e72132
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0822b21844
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@ -291,7 +291,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
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BigInteger pos = BigInteger(i) + offset;
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if (pos < 0)
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result.bits[i] = RTLIL::State::S0;
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else if (pos >= arg1.bits.size())
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else if (pos >= BigInteger(arg1.bits.size()))
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result.bits[i] = sign_ext ? arg1.bits.back() : RTLIL::State::S0;
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else
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result.bits[i] = arg1.bits[pos.toInt()];
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@ -342,7 +342,7 @@ static RTLIL::Const const_shift_shiftx(const RTLIL::Const &arg1, const RTLIL::Co
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for (int i = 0; i < result_len; i++) {
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BigInteger pos = BigInteger(i) + offset;
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if (pos < 0 || pos >= arg1.bits.size())
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if (pos < 0 || pos >= BigInteger(arg1.bits.size()))
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result.bits[i] = other_bits;
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else
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result.bits[i] = arg1.bits[pos.toInt()];
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