tangxifan
|
a1f8b3c441
|
[core] fixed a bug on bitstream generator on supporting group_config_block
|
2023-08-05 21:58:03 -07:00 |
|
tangxifan
|
68f07d6fc9
|
[core] code format
|
2023-08-05 20:53:58 -07:00 |
|
tangxifan
|
f4d7ad2bd1
|
[core] trying to fix the bug on instance naming so that bitstream generation can work
|
2023-08-05 13:38:51 -07:00 |
|
tangxifan
|
9a23dc7bff
|
[core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block
|
2023-08-04 21:20:21 -07:00 |
|
tangxifan
|
7d8d686f74
|
[core] add status codes to build grid modules
|
2023-08-04 16:52:43 -07:00 |
|
tangxifan
|
bb9cf6dbcb
|
[core] fixed a critical bug which causes undriven nets on config bus in group config block
|
2023-08-04 16:45:15 -07:00 |
|
tangxifan
|
64c0839e30
|
[core] now verilog writer supports memory group modules
|
2023-08-04 16:11:33 -07:00 |
|
tangxifan
|
a0f81a5bf2
|
[core] now verilog generator can output feedthrough memory module to files
|
2023-08-04 13:34:38 -07:00 |
|
tangxifan
|
5bc8925c3a
|
[core] fixed multiple bugs on fabric generator on supporting group_config_block
|
2023-08-04 12:36:59 -07:00 |
|
tangxifan
|
3c2518ac70
|
[core] adding debugging message when verbose is enabled
|
2023-08-04 11:20:05 -07:00 |
|
tangxifan
|
99bda2e5b0
|
[core] debugging
|
2023-08-03 22:50:14 -07:00 |
|
tangxifan
|
2aeeb0cacf
|
[core] fixed a bug which causes reg tests failed
|
2023-08-03 22:13:27 -07:00 |
|
tangxifan
|
d3895c3dc0
|
[core] code format
|
2023-08-03 17:34:25 -07:00 |
|
tangxifan
|
f4cbc95053
|
[core] syntax
|
2023-08-03 17:33:57 -07:00 |
|
tangxifan
|
5618f1d567
|
[core] now bitgen uses config child types
|
2023-08-03 16:06:19 -07:00 |
|
tangxifan
|
3331540ed6
|
[core] using config child type in bitstream generation
|
2023-08-03 14:24:22 -07:00 |
|
tangxifan
|
2facde2097
|
[core] reworked fabric generator to use config child type
|
2023-08-03 12:57:50 -07:00 |
|
tangxifan
|
5895a1d96b
|
[core] reworking fabric generator based on latest changes on configurable children
|
2023-08-02 22:50:19 -07:00 |
|
tangxifan
|
27cae41123
|
[core] rework physical and logical types of configurable child
|
2023-08-02 20:37:27 -07:00 |
|
tangxifan
|
87f2822ef8
|
[core] working on logical and physical children
|
2023-08-02 19:46:27 -07:00 |
|
tangxifan
|
c05f12ac11
|
[core] sync up logical-to-physical configurable child mapping after physical memory build-up
|
2023-08-02 12:24:16 -07:00 |
|
tangxifan
|
470ab84489
|
[core] developing group config block support for routing module
|
2023-08-01 22:57:22 -07:00 |
|
tangxifan
|
53050b94ab
|
[core] developing memory group modules in grid modules
|
2023-08-01 17:50:03 -07:00 |
|
tangxifan
|
23643f3fb1
|
[core] developing the physical memory block builder
|
2023-07-31 22:57:26 -07:00 |
|
tangxifan
|
2d2b8f67aa
|
[core] adding new option '--group_config_block' to command 'build_fabric'
|
2023-07-31 17:32:48 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
156cb800aa
|
[core] fixed a critical bug which causes wrong connections in tile modules
|
2023-07-27 12:22:16 -07:00 |
|
tangxifan
|
dd486f5ccb
|
[core] fixed a bug on checking if cb is in a tile
|
2023-07-27 11:14:05 -07:00 |
|
tangxifan
|
cfec6c88f1
|
[core] fixed a bug in cb instance naming
|
2023-07-27 10:59:46 -07:00 |
|
tangxifan
|
be0715a81c
|
[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules
|
2023-07-27 10:42:56 -07:00 |
|
tangxifan
|
97219fd825
|
[core] add more verbose to help debug failed test cases
|
2023-07-26 23:26:11 -07:00 |
|
tangxifan
|
83428a209e
|
[core] fixed a bug on io indexing which causes tile-based test cases failed in dv
|
2023-07-25 16:03:50 -07:00 |
|
tangxifan
|
6ecbbb3a94
|
[core] fixed a bug in fabric bitgen due to tile modules
|
2023-07-25 14:49:12 -07:00 |
|
tangxifan
|
64698443c9
|
[core] fixed a bug on io location map for tile modules
|
2023-07-24 22:11:57 -07:00 |
|
tangxifan
|
2105abdbca
|
[core] fixed a bug
|
2023-07-24 21:26:29 -07:00 |
|
tangxifan
|
e7d714b94d
|
[core] fixed a bug on the tile module port addition: some grid output was not pulled out
|
2023-07-24 21:21:25 -07:00 |
|
tangxifan
|
b8d080b08e
|
[core] fixed a bug where undriven cb ports are not connected to tile
|
2023-07-24 20:40:25 -07:00 |
|
tangxifan
|
3745897ff6
|
[core] fixed a few bugs
|
2023-07-24 16:10:29 -07:00 |
|
tangxifan
|
48b0ba8b78
|
[core] format
|
2023-07-24 15:00:26 -07:00 |
|
tangxifan
|
4294914987
|
[core] fixed compiler warnings
|
2023-07-24 14:59:43 -07:00 |
|
tangxifan
|
812473ef04
|
[core] fixed the bug on io location map for tiled top module
|
2023-07-24 14:50:39 -07:00 |
|
tangxifan
|
da36b735c6
|
[core] syntax
|
2023-07-24 12:13:45 -07:00 |
|
tangxifan
|
f031148959
|
[core] syntax
|
2023-07-23 22:39:36 -07:00 |
|
tangxifan
|
f551188d0f
|
[core] developed tile directs to support tile modules
|
2023-07-23 21:45:45 -07:00 |
|
tangxifan
|
14666f3ae5
|
[core] sync
|
2023-07-23 20:45:59 -07:00 |
|
tangxifan
|
0b3b7b5472
|
[core] hotfix
|
2023-07-23 13:39:06 -07:00 |
|
tangxifan
|
1ee7448070
|
[core] supporting tile annotation (for global port) in tile modules
|
2023-07-23 13:38:16 -07:00 |
|
tangxifan
|
399259ea1d
|
[core] adding prog clock arch support for tile modules
|
2023-07-23 13:11:13 -07:00 |
|
tangxifan
|
0f3f4b0d81
|
[core] now tile module use unique port name (for heterogeneous blocks)
|
2023-07-22 23:55:54 -07:00 |
|
tangxifan
|
003d9515ff
|
[core] developing tile-based top module builder
|
2023-07-22 17:13:30 -07:00 |
|
tangxifan
|
93c5a68592
|
[core] developing top-level nets for tiles
|
2023-07-21 23:21:53 -07:00 |
|
tangxifan
|
fcf308fcd6
|
[core] developing inter-tile connections for top module
|
2023-07-20 23:00:35 -07:00 |
|
tangxifan
|
b70f7fb1b6
|
[core] now option conflicts in command 'build_fabric' can error out
|
2023-07-20 21:22:07 -07:00 |
|
tangxifan
|
6b92299e39
|
[core] start working on the net build-up for tile instances under the top-level module
|
2023-07-20 17:38:13 -07:00 |
|
tangxifan
|
88c5d122ca
|
[core] syntax
|
2023-07-20 17:12:10 -07:00 |
|
tangxifan
|
db179ec4bb
|
[core] split tile instance builder and the classic fine-grained builder
|
2023-07-20 17:07:07 -07:00 |
|
tangxifan
|
ef214f4590
|
[core] code format
|
2023-07-20 17:00:29 -07:00 |
|
tangxifan
|
6458580e3e
|
[core] move child instance builder to a separated source file as these codes are expanding in size
|
2023-07-20 16:59:39 -07:00 |
|
tangxifan
|
bd265334b5
|
[core] added tile instances to top module builder
|
2023-07-19 23:26:55 -07:00 |
|
tangxifan
|
a06b9a0f48
|
[core] now start to develop the tile instances under the top module
|
2023-07-19 22:22:07 -07:00 |
|
tangxifan
|
2e69eebea0
|
[core] now tile module builder is working
|
2023-07-19 17:23:44 -07:00 |
|
tangxifan
|
0d03d7b483
|
[core] now fabric tile cache both grid and gsb coord for pb
|
2023-07-19 17:20:53 -07:00 |
|
tangxifan
|
778d03610c
|
[core] debugging
|
2023-07-19 15:27:05 -07:00 |
|
tangxifan
|
001b3b3f8b
|
[core] debugging
|
2023-07-19 14:38:07 -07:00 |
|
tangxifan
|
d03fa92ddf
|
[core] debugging
|
2023-07-19 12:49:35 -07:00 |
|
tangxifan
|
48e207d3e4
|
[core] debugging
|
2023-07-19 12:22:57 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
|
tangxifan
|
5ae146bd86
|
[core] finish up tile module builder
|
2023-07-18 21:17:40 -07:00 |
|
tangxifan
|
0dcec9d8e5
|
[core] finishing up tile module builder
|
2023-07-18 17:56:27 -07:00 |
|
tangxifan
|
403ed4ea60
|
[core] still developing tile module port and net builder
|
2023-07-18 16:03:47 -07:00 |
|
tangxifan
|
aabcc25567
|
[core] developing tile module port and net builder
|
2023-07-17 23:06:55 -07:00 |
|
tangxifan
|
ba4b7e3522
|
[core] developing tile module builder
|
2023-07-16 15:18:09 -07:00 |
|
tangxifan
|
98c598cec2
|
[core] unique tile identifier done
|
2023-07-15 22:54:33 -07:00 |
|
tangxifan
|
ea8d128789
|
[core] syntax
|
2023-07-15 20:29:21 -07:00 |
|
tangxifan
|
c2ef5ca408
|
[core] developing top-left style tile info
|
2023-07-14 22:48:44 -07:00 |
|
tangxifan
|
3de4d3fc09
|
[core] add a new command 'write_fabric_key' and now writer supports module-level keys
|
2023-07-08 18:12:51 -07:00 |
|
tangxifan
|
433391eec4
|
[core] move new functions to a separated source file
|
2023-07-07 15:03:03 -07:00 |
|
tangxifan
|
d3aa4c53d0
|
[core] now support rebuild configuarable children for ccff submodules
|
2023-07-07 14:51:21 -07:00 |
|
tangxifan
|
d3109ee88b
|
[core] developing configurable children reloading from fabric key
|
2023-07-06 21:53:22 -07:00 |
|
tangxifan
|
987a562e0f
|
[core] fixed the bug when checking mapping status of fpga core ports
|
2023-06-23 17:21:52 -07:00 |
|
tangxifan
|
463332c77a
|
[core] code complete for adding nets between top and core module
|
2023-06-23 13:21:25 -07:00 |
|
tangxifan
|
b30148f8fb
|
[core] apply more sanity checks on top module port
|
2023-06-23 12:37:46 -07:00 |
|
tangxifan
|
2484150ab6
|
[core] working on port addition to top module
|
2023-06-23 12:21:47 -07:00 |
|
tangxifan
|
8bd9ae02fd
|
[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
|
tangxifan
|
7961223eac
|
[core] enabling io naming rules in fabric builder
|
2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
a4f26798b0
|
[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc
|
2023-06-19 11:59:48 -07:00 |
|
tangxifan
|
63ee0c980e
|
[core] fixed some bugs
|
2023-06-18 22:12:54 -07:00 |
|
tangxifan
|
d9499f2b40
|
[core] now fpga bitstream supports the wrapper module
|
2023-06-18 21:58:36 -07:00 |
|
tangxifan
|
c7ade72200
|
[core] code complete for the core wrapper creator. Start debugging
|
2023-06-18 19:17:42 -07:00 |
|
tangxifan
|
8bc70b590a
|
[core] developing fpga_core insertion
|
2023-06-17 23:42:45 -07:00 |
|
tangxifan
|
ee59bdb675
|
[core] code format
|
2023-06-07 18:55:34 -07:00 |
|
tangxifan
|
327f7f4dab
|
[core] now adapt to latest API of DeviceGrid
|
2023-06-07 18:54:48 -07:00 |
|
tangxifan
|
dab89322b3
|
[core] fixed the bug in I/O location map build-up when supporting subtiles
|
2023-05-04 09:51:05 +08:00 |
|
tangxifan
|
cb0e6b9e17
|
[core] fixed a critical bug
|
2023-05-03 21:46:35 +08:00 |
|
tangxifan
|
6c48c57421
|
[core] fixed some bugs in the subtile support
|
2023-05-03 21:23:52 +08:00 |
|
tangxifan
|
7bedc965ac
|
[core] supporting subtile
|
2023-05-03 17:30:58 +08:00 |
|
tangxifan
|
28b7a12f68
|
[core] code format
|
2023-04-23 14:31:35 +08:00 |
|
tangxifan
|
bd511ba515
|
[core] fixed syntax errors
|
2023-04-23 14:26:08 +08:00 |
|
tangxifan
|
592765af48
|
[core] code complete for upgrading netlist generator w.r.t. ccff v2
|
2023-04-23 13:57:37 +08:00 |
|
tangxifan
|
5500b9a289
|
[core] upgrading netlist generator
|
2023-04-22 16:27:27 +08:00 |
|
tangxifan
|
46510388be
|
[core] now fabric generator can wire clock ports to routing blocks
|
2023-03-02 12:33:26 -08:00 |
|
tangxifan
|
974263f0fa
|
[core] dev
|
2023-03-01 23:27:29 -08:00 |
|
tangxifan
|
099d9f32f4
|
[core] dev
|
2023-03-01 16:08:15 -08:00 |
|
tangxifan
|
afdc071c4c
|
[engine] apply code format
|
2022-10-06 18:13:33 -07:00 |
|
tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
|
2022-10-06 18:08:57 -07:00 |
|
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
|
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
|
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
|
tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
|
tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
|
tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
|
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
|
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
|
tangxifan
|
9e1abf5898
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 21:39:14 -07:00 |
|
tangxifan
|
d3f08a893c
|
[engine] now frame view will not build nets for configuration bus
|
2022-09-01 20:02:00 -07:00 |
|
tangxifan
|
0c2b49ddb9
|
[engine] remove debugging log output
|
2022-08-27 13:06:05 -07:00 |
|
tangxifan
|
b3e4a06969
|
[engine] adapt vpr wrapper to the latest main.cpp from vtr
|
2022-08-23 14:28:05 -07:00 |
|
tangxifan
|
892770a8fb
|
[engine] debugging subtile index failures
|
2022-08-23 14:13:10 -07:00 |
|
tangxifan
|
0a6b794ef0
|
[engine] fixed bugs in subtiles. Revisited the usage of client functions
|
2022-08-23 12:35:04 -07:00 |
|
tangxifan
|
019e663e12
|
[engine] fixing the bugs on building global nets to sub tile pins
|
2022-08-23 11:58:44 -07:00 |
|
tangxifan
|
e0ae851e28
|
[engine] correcting compilation errors due to vpr upgrade
|
2022-08-17 16:25:12 -07:00 |
|
tangxifan
|
ce32c3b30b
|
[engine] fixing api errors
|
2022-08-17 14:47:14 -07:00 |
|
tangxifan
|
3c2bf5159b
|
[engine] use new API to get node side
|
2022-08-17 14:38:40 -07:00 |
|
tangxifan
|
8f1aac885e
|
[engine] fixing mismatches in APIs
|
2022-08-17 14:19:02 -07:00 |
|
tangxifan
|
0c329866da
|
[engine] Use RRGraphView in openfpga source codes
|
2022-08-16 16:48:32 -07:00 |
|
tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
|
tangxifan
|
6586ea7816
|
[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
|
2021-10-11 09:40:02 -07:00 |
|
tangxifan
|
b9c540ec3f
|
[Engine] Upgrade fabric key writer to support BL/WL shift register banks
|
2021-10-10 21:14:14 -07:00 |
|
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
|
tangxifan
|
aac74d9163
|
[Engine] Bug fix
|
2021-10-09 18:46:20 -07:00 |
|
tangxifan
|
fa08f44107
|
[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
|
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
|
tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
|
2021-10-08 22:00:01 -07:00 |
|
tangxifan
|
e3ff40d9e0
|
[Engine] Add missing return value
|
2021-10-08 20:17:55 -07:00 |
|
tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
|
2021-10-08 17:58:06 -07:00 |
|
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
|
tangxifan
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f7484d4323
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[Engine] Update the key memory data structure to contain shift register bank general information
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2021-10-08 10:42:18 -07:00 |
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tangxifan
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3efd6840a8
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[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
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2021-10-04 16:58:01 -07:00 |
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tangxifan
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28904ff526
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[Engine] Bug fix on wrong port type for shift register chains
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2021-10-03 12:31:58 -07:00 |
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tangxifan
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477c1cd062
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[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
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2021-10-01 17:38:26 -07:00 |
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tangxifan
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977d81679d
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[Engine] Upgrade check codes for WL CCFF
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2021-10-01 17:23:10 -07:00 |
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tangxifan
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cf96d9ff01
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[Engine] Add programming shift register clock to internal global port data structure
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2021-10-01 11:05:31 -07:00 |
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tangxifan
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7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
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tangxifan
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4bdff1554d
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[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
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2021-09-30 21:20:56 -07:00 |
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tangxifan
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33972fc0ec
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[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
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2021-09-30 21:05:41 -07:00 |
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tangxifan
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f456c7e236
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[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
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2021-09-29 20:34:25 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |