Commit Graph

408 Commits

Author SHA1 Message Date
tangxifan eeaa3373c6 [core] code format 2024-08-02 17:48:47 -07:00
tangxifan 82cf7bbb8c [core] Add verbose mode on find_node() for clock rr graph 2024-08-02 17:47:41 -07:00
tangxifan d6db51f29e [core] code format 2024-07-30 19:09:31 -07:00
tangxifan ef6b6f8e40 [core] remove warnings 2024-07-30 18:50:49 -07:00
tangxifan ae95357991 [core] code format 2024-07-30 15:40:41 -07:00
tangxifan a2c3af60d7 [core] fixed a bug where unique cb module is not considered as entry point 2024-07-30 15:39:44 -07:00
tangxifan 853883cd36 [core] code format 2024-07-30 12:56:03 -07:00
tangxifan 18d12109fb [core] fixed a critical bug where cb port name using index is not considered on clock network entry 2024-07-16 17:42:21 -07:00
tangxifan cbd10e1222 [core] fixed a bug where tile module's global port is not derived from dedicated clock network 2024-07-16 16:58:21 -07:00
tangxifan 092b8b038f [core] remove verbose out 2024-07-08 22:23:37 -07:00
tangxifan 04504e4d5d [core] code format 2024-07-08 22:22:59 -07:00
tangxifan 1cdb1c5995 [core] fixed a bug on calculating subtile pins 2024-07-08 22:22:08 -07:00
tangxifan fe06c2f2b1 [core] code format 2024-07-08 16:18:58 -07:00
tangxifan 7bd60f5f7d [core] support perimeter cb when identify pins of I/Os tiles 2024-07-08 12:39:54 -07:00
tangxifan 703cbddc9e [core] code format 2024-07-06 12:14:57 -07:00
tangxifan 6024e35f89 [core] fixed a bug 2024-07-05 18:50:14 -07:00
tangxifan 1f7fbfef64 [core] fixed a bug on inter-tile connections in top module 2024-07-05 18:19:22 -07:00
tangxifan e95b264965 [core] debugging 2024-07-05 18:08:48 -07:00
tangxifan cca9fb4756 [core] fixed a bug on bottom left tile organization 2024-07-05 17:55:19 -07:00
tangxifan 46d916f0a0 [core] fixed the bugs in fabric tile build-up 2024-07-05 16:59:08 -07:00
tangxifan a41f437109 [core] now netlist look ok 2024-07-05 12:36:47 -07:00
tangxifan 6d798897fd [lib] update vtr 2024-07-04 14:46:57 -07:00
tangxifan f560fb8381 [core] more verbose 2024-07-04 14:27:17 -07:00
tangxifan a8850d4f0f [core] now verbose mode is applicable to more build top module cb instances 2024-07-04 14:22:30 -07:00
tangxifan 4b53e57c92 [core] fixed a bug 2024-07-04 13:33:04 -07:00
tangxifan d2a68ff9c5 [core] now corner tile are considered as config child 2024-07-04 13:25:57 -07:00
tangxifan b80ed8d15c [core] fixed a bug 2024-07-04 12:58:16 -07:00
tangxifan a3723b33b3 [core] fixed a minor bug 2024-07-04 12:52:29 -07:00
tangxifan a717882304 [core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks 2024-07-04 12:44:48 -07:00
tangxifan 724c14d1f7 [core] fixed a bug on build top module connections on perimeter gsb when cbs occur 2024-07-04 11:09:01 -07:00
tangxifan 3afb92d6a5 [core] code format 2024-06-30 22:48:15 -07:00
tangxifan 1fd974d544 [core] fixed a bug where clock network size cannot impact global port on top module 2024-06-29 17:35:47 -07:00
tangxifan 52ae484a7c [core] fixed a bug on messed up wire connections for OPINs 2024-05-20 13:50:31 -07:00
tangxifan b554a3d855 [core] code format 2024-05-19 17:24:38 -07:00
tangxifan 56aaa6a1f4 [core] sytax 2024-05-19 17:23:48 -07:00
tangxifan 065d77c679 [core] supporting opin connection to cb in tiles 2024-05-19 17:04:24 -07:00
tangxifan 9079056871 [core] now connect OPIN to CB in top-level module 2024-05-19 14:27:36 -07:00
tangxifan 918bf79ca3 [core] update vtr and developing caches for OPIN lists just for connection blocks 2024-05-19 14:10:00 -07:00
tangxifan 772da3006b [core] code format 2024-05-18 22:19:17 -07:00
tangxifan 304f34525e [core] syntax 2024-05-18 22:17:52 -07:00
tangxifan b533ea4060 [core] now cb module include OPIN nodes 2024-05-18 22:00:02 -07:00
tangxifan 3d8107487c [core] code format 2024-05-03 10:21:39 -07:00
tangxifan c7501cb9b7 [core] fixed the bugs when there are module renaming 2024-05-03 10:20:19 -07:00
tangxifan f41a5e8b89 [core] fixed some bugs 2024-05-02 22:49:06 -07:00
tangxifan c557b0104a [core] avoid unwanted tab 2024-05-02 21:34:12 -07:00
tangxifan b85ec28eb8 [core] code format 2024-05-02 21:17:17 -07:00
tangxifan d3b1e562ad [core] fixed some bugs on format 2024-05-02 21:11:20 -07:00
tangxifan bf24382f19 [core] code format 2024-05-02 18:33:07 -07:00
tangxifan a2fb84dfa9 [core] add fabric hierarchy writer 2024-05-02 18:30:20 -07:00
tangxifan 4d3447f773 [core] rework fabric hierarchy writer 2024-05-02 18:05:38 -07:00