[core] fixed the bugs in fabric tile build-up
This commit is contained in:
tangxifan
parent
5e89b950ed
commit
46d916f0a0
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@ -22,12 +22,110 @@
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namespace openfpga {
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/********************************************************************
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* Build tiles by following the top-level style.
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* - The programmble block, e.g., clb, is placed on the top-left corner
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* - The connection blocks and switch block are placed on the right and bottom
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*sides
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* With a given coordinate of a grid, find an existing fabric tile
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* or create a new fabric tile
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* - A grid may never exist in any fabric tile (no coordinate matches)
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* Create a new one
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* - A grid already in another fabric tile (occur in heterogeneous blocks)
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* Find the existing one
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*******************************************************************/
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static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
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static int find_or_create_one_fabric_tile_from_grid(
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FabricTile& fabric_tile,
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FabricTileId& curr_tile_id,
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const DeviceGrid& grids,
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const t_physical_tile_loc& tile_loc,
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const RRGraphView& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& verbose) {
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t_physical_tile_type_ptr phy_tile_type =
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grids.get_physical_type(tile_loc);
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vtr::Point<size_t> curr_tile_coord(tile_loc.x, tile_loc.y);
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vtr::Point<size_t> curr_gsb_coord(tile_loc.x, tile_loc.y);
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bool skip_add_pb = false;
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/* For EMPTY grid, routing blocks may still be required if there is a gsb
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*/
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if (true == is_empty_type(phy_tile_type)) {
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skip_add_pb = true;
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if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
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VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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return CMD_EXEC_SUCCESS;
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}
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/* Need to create a new tile here */
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VTR_LOGV(verbose,
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"Create tile[%lu][%lu] which only has routing but not a "
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"programmable block\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
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} else if ((0 < grids.get_width_offset(tile_loc)) ||
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(0 < grids.get_height_offset(tile_loc))) {
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/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
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/* Find the root of this grid, the instance id should be valid.
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* We just copy it here
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*/
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vtr::Point<size_t> root_tile_coord(
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curr_tile_coord.x() - grids.get_width_offset(tile_loc),
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curr_tile_coord.y() - grids.get_height_offset(tile_loc));
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skip_add_pb = true;
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VTR_LOGV(verbose,
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"Tile[%lu][%lu] contains a heterogeneous block which is "
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"rooted from tile[%lu][%lu]\n",
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curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(),
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root_tile_coord.y());
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curr_tile_id = fabric_tile.find_tile(root_tile_coord);
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/* Update the coordinates of the pb in tiles */
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size_t root_pb_idx_in_curr_tile =
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fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord);
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int status_code = fabric_tile.set_pb_max_coordinate(
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curr_tile_id, root_pb_idx_in_curr_tile, curr_tile_coord);
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if (status_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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} else {
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/* Need to create a new tile here */
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VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
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}
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/* Ensure that we have a valid id */
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if (!fabric_tile.valid_tile_id(curr_tile_id)) {
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VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Add components: pb, cbx, cby, and sb if exists */
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if (!skip_add_pb) {
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fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord,
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curr_gsb_coord);
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}
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Build tiles by following the bottom style.
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* - The programmble block, e.g., clb, is placed on the bottom-left corner
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* - The connection blocks and switch block are placed on the top and bottom
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*sides
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* This is exactly how GSB is organized. Just need to transfer data from one GSB
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* The gsb coordinate is the same as the grid coordinate when the
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* bottom-left style is considered
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*
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* ------------------------------
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* +----------+ +----------+ ^
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* | CBx | | SB | |
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* | [x][y] | | [x][y] | GSB[x][y]
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* +----------+ +----------+ |
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* +----------+ +----------+ |
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* | Grid | | CBy | |
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* | [x][y] | | [x][y] | |
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* +----------+ +----------+ v
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* ------------------------------
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*
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*******************************************************************/
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static int build_fabric_tile_style_bottom_left(FabricTile& fabric_tile,
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const DeviceGrid& grids,
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const size_t& layer,
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const RRGraphView& rr_graph,
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@ -39,82 +137,16 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
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for (size_t ix = 0; ix < grids.width(); ++ix) {
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for (size_t iy = 0; iy < grids.height(); ++iy) {
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t_physical_tile_loc tile_loc(ix, iy, layer);
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t_physical_tile_type_ptr phy_tile_type =
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grids.get_physical_type(tile_loc);
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bool skip_add_pb = false;
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vtr::Point<size_t> curr_tile_coord(ix, iy);
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vtr::Point<size_t> curr_gsb_coord(ix, iy - 1);
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FabricTileId curr_tile_id = FabricTileId::INVALID();
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/* For EMPTY grid, routing blocks may still be required if there is a gsb
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*/
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if (true == is_empty_type(phy_tile_type)) {
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skip_add_pb = true;
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if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
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VTR_LOGV(verbose, "Skip tile[%lu][%lu] as it is empty\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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continue;
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}
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/* Need to create a new tile here */
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VTR_LOGV(verbose,
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"Create tile[%lu][%lu] which only has routing but not a "
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"programmable block\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
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} else if ((0 < grids.get_width_offset(tile_loc)) ||
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(0 < grids.get_height_offset(tile_loc))) {
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/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
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/* Find the root of this grid, the instance id should be valid.
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* We just copy it here
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*/
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vtr::Point<size_t> root_tile_coord(
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ix - grids.get_width_offset(tile_loc),
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iy - grids.get_height_offset(tile_loc));
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skip_add_pb = true;
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VTR_LOGV(verbose,
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"Tile[%lu][%lu] contains a heterogeneous block which is "
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"rooted from tile[%lu][%lu]\n",
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curr_tile_coord.x(), curr_tile_coord.y(), root_tile_coord.x(),
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root_tile_coord.y());
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curr_tile_id = fabric_tile.find_tile(root_tile_coord);
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/* Update the coordinates of the pb in tiles */
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size_t root_pb_idx_in_curr_tile =
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fabric_tile.find_pb_index_in_tile(curr_tile_id, root_tile_coord);
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status_code = fabric_tile.set_pb_max_coordinate(
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curr_tile_id, root_pb_idx_in_curr_tile, vtr::Point<size_t>(ix, iy));
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if (status_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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} else {
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/* Need to create a new tile here */
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VTR_LOGV(verbose, "Create a regular tile[%lu][%lu]\n",
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curr_tile_coord.x(), curr_tile_coord.y());
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curr_tile_id = fabric_tile.create_tile(curr_tile_coord);
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}
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/* Ensure that we have a valid id */
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if (!fabric_tile.valid_tile_id(curr_tile_id)) {
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VTR_LOG_ERROR("Failed to get a valid id for tile[%lu][%lu]!\n", ix, iy);
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status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose);
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if (status_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Add components: pb, cbx, cby, and sb if exists */
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if (!skip_add_pb) {
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fabric_tile.add_pb_coordinate(curr_tile_id, curr_tile_coord,
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curr_gsb_coord);
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/* If no valid tile is created or spotted, the tile does not exist physically, skip */
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if (fabric_tile.valid_tile_id(curr_tile_id)) {
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continue;
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}
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/* The gsb coordinate is different than the grid coordinate when the
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* top-left style is considered
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*
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* +----------+ +----------+
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* | Grid | | CBx |
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* | [x][y] | | [x][y] |
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* +----------+ +----------+
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* +----------+ +----------+
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* | CBy | | SB |
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* | [x][y-1] | | [x][y-1] |
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* +----------+ +----------+
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*
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*/
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vtr::Point<size_t> curr_gsb_coord(ix, iy);
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if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
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continue;
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}
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@ -135,6 +167,77 @@ static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
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return status_code;
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}
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/********************************************************************
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* Build tiles by following the top-left style.
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* - The programmble block, e.g., clb, is placed on the top-left corner
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* - The connection blocks and switch block are placed on the right and bottom
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*sides
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* Tile[x][y]
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* ------------------------------
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* +----------+ +----------+ ^
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* | Grid | | CBy | GSB[x][y]
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* | [x][y] | | [x][y] | |
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* +----------+ +----------+ v
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* ------------------------------
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* +----------+ +----------+ ^
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* | CBx | | SB | |
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* | [x][y-1] | | [x][y-1] | GSB[x][y-1]
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* +----------+ +----------+ |
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* ------------------------------
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*******************************************************************/
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static int build_fabric_tile_style_top_left(FabricTile& fabric_tile,
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const DeviceGrid& grids,
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const size_t& layer,
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const RRGraphView& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const bool& verbose) {
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int status_code = CMD_EXEC_SUCCESS;
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/* Walk through all the device rr_gsb and create tile one by one */
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for (size_t ix = 0; ix < grids.width(); ++ix) {
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for (size_t iy = 0; iy < grids.height(); ++iy) {
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t_physical_tile_loc tile_loc(ix, iy, layer);
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FabricTileId curr_tile_id = FabricTileId::INVALID();
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status_code = find_or_create_one_fabric_tile_from_grid(fabric_tile, curr_tile_id, grids, tile_loc, rr_graph, device_rr_gsb, verbose);
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if (status_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* If no valid tile is created or spotted, the tile does not exist physically, skip */
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if (fabric_tile.valid_tile_id(curr_tile_id)) {
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continue;
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}
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/* For the cby in the same gsb */
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vtr::Point<size_t> curr_gsb_coord(ix, iy);
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if (!device_rr_gsb.is_gsb_exist(rr_graph, curr_gsb_coord)) {
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continue;
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}
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const RRGSB& curr_rr_gsb = device_rr_gsb.get_gsb(curr_gsb_coord);
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if (curr_rr_gsb.is_cb_exist(CHANY)) {
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fabric_tile.add_cb_coordinate(curr_tile_id, CHANY,
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curr_rr_gsb.get_sb_coordinate());
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}
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/* For the cbx and sb in the neighbour gsb */
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vtr::Point<size_t> neighbor_gsb_coord(ix, iy - 1);
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if (!device_rr_gsb.is_gsb_exist(rr_graph, neighbor_gsb_coord)) {
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continue;
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}
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const RRGSB& neighbor_rr_gsb = device_rr_gsb.get_gsb(neighbor_gsb_coord);
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if (neighbor_rr_gsb.is_cb_exist(CHANX)) {
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fabric_tile.add_cb_coordinate(curr_tile_id, CHANX,
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neighbor_rr_gsb.get_sb_coordinate());
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}
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if (neighbor_rr_gsb.is_sb_exist(rr_graph)) {
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fabric_tile.add_sb_coordinate(curr_tile_id,
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neighbor_rr_gsb.get_sb_coordinate());
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}
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}
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}
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return status_code;
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}
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/********************************************************************
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* Build tile-level information for a given FPGA fabric, w.r.t. to configuration
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*******************************************************************/
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@ -152,6 +255,10 @@ int build_fabric_tile(FabricTile& fabric_tile, const TileConfig& tile_config,
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if (tile_config.style() == TileConfig::e_style::TOP_LEFT) {
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status_code = build_fabric_tile_style_top_left(
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fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose);
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} else if (tile_config.style() == TileConfig::e_style::BOTTOM_LEFT) {
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status_code = build_fabric_tile_style_bottom_left(
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fabric_tile, grids, 0, rr_graph, device_rr_gsb, verbose);
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} else {
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/* Error out for styles that are not supported yet! */
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VTR_LOG_ERROR("Tile style '%s' is not supported yet!\n",
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@ -732,13 +732,13 @@ static int build_tile_module_port_and_nets_between_sb_and_cb(
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* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
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* use is_cb_exist()
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*/
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if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
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if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
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if (false == rr_gsb.is_cb_exist(cb_type)) {
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continue;
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}
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}
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if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
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if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
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const RRGSB& adjacent_gsb =
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device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
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if (false == adjacent_gsb.is_cb_exist(cb_type)) {
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