[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
This commit is contained in:
parent
48590df452
commit
a717882304
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@ -128,7 +128,7 @@ int build_device_module_graph(
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openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
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openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib,
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sram_model, openfpga_ctx.arch().config_protocol.type(),
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name_module_using_index, frame_view, verbose);
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name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose);
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}
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/* Build FPGA fabric top-level module */
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@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports(
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ModuleManager& module_manager, const ModuleId& grid_module,
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side) {
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const bool& perimeter_cb) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
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@ -66,7 +67,7 @@ void add_grid_module_duplicated_pb_type_ports(
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides =
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find_grid_module_pin_sides(grid_type_descriptor, border_side);
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find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb);
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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@ -172,7 +173,9 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
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const size_t& child_inst_subtile_index,
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
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const e_side& border_side,
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const bool& perimeter_cb,
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const e_pin2pin_interc_type& pin2pin_interc_type) {
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/* Make sure this is ONLY applied to output pins */
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VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type);
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@ -183,7 +186,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin(
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides =
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find_grid_module_pin_sides(grid_type_descriptor, border_side);
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find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb);
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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@ -316,7 +319,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
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const ModuleId& child_module, const size_t& child_instance,
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const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side) {
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const bool& perimeter_cb) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
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@ -334,7 +338,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
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border_side, INPUT2INPUT_INTERC);
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border_side, perimeter_cb, INPUT2INPUT_INTERC);
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}
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}
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@ -345,7 +349,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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&(top_pb_graph_node->output_pins[iport][ipin]), border_side,
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OUTPUT2OUTPUT_INTERC);
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perimeter_cb, OUTPUT2OUTPUT_INTERC);
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}
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}
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@ -356,7 +360,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
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border_side, INPUT2INPUT_INTERC);
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border_side, perimeter_cb, INPUT2INPUT_INTERC);
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}
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}
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}
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@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports(
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ModuleManager& module_manager, const ModuleId& grid_module,
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side);
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const bool& perimeter_cb);
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void add_grid_module_nets_connect_duplicated_pb_type_ports(
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ModuleManager& module_manager, const ModuleId& grid_module,
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const ModuleId& child_module, const size_t& child_instance,
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const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side);
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const bool& perimeter_cb);
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} /* end namespace openfpga */
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@ -24,7 +24,7 @@ namespace openfpga {
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* 5. I/O grids in the center part of FPGA can have ports on any side
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*******************************************************************/
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std::vector<e_side> find_grid_module_pin_sides(
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t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) {
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t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) {
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/* We must have an regular (non-I/O) type here */
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VTR_ASSERT(true == is_io_type(grid_type_descriptor));
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SideManager side_manager(border_side);
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@ -33,7 +33,16 @@ std::vector<e_side> find_grid_module_pin_sides(
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return {TOP, RIGHT, BOTTOM, LEFT};
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}
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return std::vector<e_side>(1, side_manager.get_opposite());
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if (!perimeter_cb) {
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return std::vector<e_side>(1, side_manager.get_opposite());
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}
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/* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */
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std::vector<e_side> pin_sides;
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pin_sides.reserve(3);
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for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) {
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pin_sides.push_back(pin_side);
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}
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return pin_sides;
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}
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/********************************************************************
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@ -47,7 +56,8 @@ void add_grid_module_net_connect_pb_graph_pin(
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) {
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const e_side& border_side, const bool& perimeter_cb,
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const e_pin2pin_interc_type& pin2pin_interc_type) {
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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@ -55,7 +65,7 @@ void add_grid_module_net_connect_pb_graph_pin(
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides =
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find_grid_module_pin_sides(grid_type_descriptor, border_side);
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find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb);
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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@ -19,7 +19,7 @@
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namespace openfpga {
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std::vector<e_side> find_grid_module_pin_sides(
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t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side);
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t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb);
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void add_grid_module_net_connect_pb_graph_pin(
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ModuleManager& module_manager, const ModuleId& grid_module,
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@ -28,7 +28,7 @@ void add_grid_module_net_connect_pb_graph_pin(
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side,
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const e_side& border_side, const bool& perimeter_cb,
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const enum e_pin2pin_interc_type& pin2pin_interc_type);
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} /* end namespace openfpga */
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@ -42,7 +42,9 @@ static void add_grid_module_pb_type_ports(
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ModuleManager& module_manager, const ModuleId& grid_module,
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const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side) {
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const TileAnnotation& tile_annotation,
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const e_side& border_side,
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const bool& perimeter_cb) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(nullptr != grid_type_descriptor);
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@ -53,7 +55,7 @@ static void add_grid_module_pb_type_ports(
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides =
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find_grid_module_pin_sides(grid_type_descriptor, border_side);
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find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb);
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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@ -125,7 +127,8 @@ static void add_grid_module_nets_connect_pb_type_ports(
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const ModuleId& child_module, const size_t& child_instance,
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const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation,
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t_physical_tile_type_ptr grid_type_descriptor,
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const TileAnnotation& tile_annotation, const e_side& border_side) {
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const bool& perimeter_cb) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(nullptr != grid_type_descriptor);
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@ -144,7 +147,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]),
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border_side, INPUT2INPUT_INTERC);
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border_side, perimeter_cb, INPUT2INPUT_INTERC);
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}
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}
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@ -155,7 +158,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]),
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border_side, OUTPUT2OUTPUT_INTERC);
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border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC);
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}
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}
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@ -166,7 +169,7 @@ static void add_grid_module_nets_connect_pb_type_ports(
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module_manager, grid_module, child_module, child_instance,
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child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor,
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tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]),
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border_side, INPUT2INPUT_INTERC);
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border_side, perimeter_cb, INPUT2INPUT_INTERC);
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}
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}
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}
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@ -1168,6 +1171,7 @@ static int build_physical_tile_module(
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const TileAnnotation& tile_annotation, const e_side& border_side,
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const QLMemoryBankConfigSetting* ql_memory_bank_config_setting,
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const bool& duplicate_grid_pin, const bool& group_config_block,
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const bool& perimeter_cb,
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const bool& verbose) {
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int status = CMD_EXEC_SUCCESS;
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/* Create a Module for the top-level physical block, and add to module manager
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@ -1247,7 +1251,7 @@ static int build_physical_tile_module(
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/* Default way to add these ports by following the definition in pb_types */
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add_grid_module_pb_type_ports(module_manager, grid_module,
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vpr_device_annotation, phy_block_type,
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tile_annotation, border_side);
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tile_annotation, border_side, perimeter_cb);
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/* Add module nets to connect the pb_type ports to sub modules */
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for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
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VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
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@ -1264,7 +1268,7 @@ static int build_physical_tile_module(
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module_manager.child_module_instances(grid_module, pb_module)) {
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add_grid_module_nets_connect_pb_type_ports(
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module_manager, grid_module, pb_module, child_instance, sub_tile,
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vpr_device_annotation, phy_block_type, tile_annotation, border_side);
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vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb);
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}
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}
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} else {
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@ -1272,7 +1276,7 @@ static int build_physical_tile_module(
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/* Add these ports with duplication */
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add_grid_module_duplicated_pb_type_ports(
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module_manager, grid_module, vpr_device_annotation, phy_block_type,
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tile_annotation, border_side);
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tile_annotation, border_side, perimeter_cb);
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/* Add module nets to connect the duplicated pb_type ports to sub modules */
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for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
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@ -1290,7 +1294,7 @@ static int build_physical_tile_module(
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module_manager.child_module_instances(grid_module, pb_module)) {
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add_grid_module_nets_connect_duplicated_pb_type_ports(
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module_manager, grid_module, pb_module, child_instance, sub_tile,
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vpr_device_annotation, phy_block_type, tile_annotation, border_side);
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vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb);
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}
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}
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}
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@ -1436,7 +1440,7 @@ int build_grid_modules(
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module_manager, decoder_lib, device_annotation, circuit_lib,
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sram_orgz_type, sram_model, &physical_tile, tile_annotation,
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io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin,
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group_config_block, verbose);
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group_config_block, device_ctx.arch->perimeter_cb, verbose);
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if (status != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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@ -1446,7 +1450,7 @@ int build_grid_modules(
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status = build_physical_tile_module(
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module_manager, decoder_lib, device_annotation, circuit_lib,
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sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES,
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ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block,
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ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb,
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verbose);
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if (status != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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@ -1175,6 +1175,7 @@ static int build_tile_port_and_nets_from_pb(
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const TileAnnotation& tile_annotation, const vtr::Point<size_t>& pb_coord,
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const std::vector<size_t>& pb_instances, const FabricTile& fabric_tile,
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const FabricTileId& curr_fabric_tile_id, const size_t& ipb,
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const bool& perimeter_cb,
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const bool& frame_view, const bool& verbose) {
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size_t pb_instance = pb_instances[ipb];
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t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
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@ -1201,7 +1202,7 @@ static int build_tile_port_and_nets_from_pb(
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* Otherwise, we will iterate all the 4 sides
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*/
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if (true == is_io_type(phy_tile)) {
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grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side);
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grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb);
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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@ -1378,6 +1379,7 @@ static int build_tile_module_ports_and_nets(
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const FabricTileId& fabric_tile_id, const std::vector<size_t>& pb_instances,
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const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
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const std::vector<size_t>& sb_instances, const bool& name_module_using_index,
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const bool& perimeter_cb,
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const bool& frame_view, const bool& verbose) {
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int status_code = CMD_EXEC_SUCCESS;
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@ -1441,7 +1443,7 @@ static int build_tile_module_ports_and_nets(
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status_code = build_tile_port_and_nets_from_pb(
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module_manager, tile_module, grids, layer, vpr_device_annotation,
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rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile,
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fabric_tile_id, ipb, frame_view, verbose);
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fabric_tile_id, ipb, perimeter_cb, frame_view, verbose);
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if (status_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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@ -1487,7 +1489,9 @@ static int build_tile_module(
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const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib,
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const CircuitModelId& sram_model,
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const e_config_protocol_type& sram_orgz_type,
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const bool& name_module_using_index, const bool& frame_view,
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const bool& name_module_using_index,
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const bool& perimeter_cb,
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const bool& frame_view,
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const bool& verbose) {
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int status_code = CMD_EXEC_SUCCESS;
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@ -1635,7 +1639,7 @@ static int build_tile_module(
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module_manager, tile_module, grids, layer, vpr_device_annotation,
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device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id,
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pb_instances, cb_instances, sb_instances, name_module_using_index,
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frame_view, verbose);
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perimeter_cb, frame_view, verbose);
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/* Add global ports to the pb_module:
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* This is a much easier job after adding sub modules (instances),
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@ -1709,6 +1713,7 @@ int build_tile_modules(ModuleManager& module_manager,
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const CircuitModelId& sram_model,
|
||||
const e_config_protocol_type& sram_orgz_type,
|
||||
const bool& name_module_using_index,
|
||||
const bool& perimeter_cb,
|
||||
const bool& frame_view, const bool& verbose) {
|
||||
vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric");
|
||||
|
||||
|
@ -1722,7 +1727,7 @@ int build_tile_modules(ModuleManager& module_manager,
|
|||
module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer,
|
||||
vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation,
|
||||
circuit_lib, sram_model, sram_orgz_type, name_module_using_index,
|
||||
frame_view, verbose);
|
||||
perimeter_cb, frame_view, verbose);
|
||||
if (status_code != CMD_EXEC_SUCCESS) {
|
||||
return CMD_EXEC_FATAL_ERROR;
|
||||
}
|
||||
|
|
|
@ -36,6 +36,7 @@ int build_tile_modules(ModuleManager& module_manager,
|
|||
const CircuitModelId& sram_model,
|
||||
const e_config_protocol_type& sram_orgz_type,
|
||||
const bool& name_module_using_index,
|
||||
const bool& perimeter_cb,
|
||||
const bool& frame_view, const bool& verbose);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
Loading…
Reference in New Issue