diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 757171c78..e03ee2510 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -128,7 +128,7 @@ int build_device_module_graph( openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph, openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib, sram_model, openfpga_ctx.arch().config_protocol.type(), - name_module_using_index, frame_view, verbose); + name_module_using_index, vpr_device_ctx.arch->perimeter_cb, frame_view, verbose); } /* Build FPGA fabric top-level module */ diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 32304bdc7..7e628e459 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,7 +55,8 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -66,7 +67,7 @@ void add_grid_module_duplicated_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -172,7 +173,9 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( const size_t& child_inst_subtile_index, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, + const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Make sure this is ONLY applied to output pins */ VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type); @@ -183,7 +186,7 @@ static void add_grid_module_net_connect_duplicated_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -316,7 +319,8 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(false == is_empty_type(grid_type_descriptor)); @@ -334,7 +338,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -345,7 +349,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, - OUTPUT2OUTPUT_INTERC); + perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -356,7 +360,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 4f2eafee2..9f95b7dd7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -21,14 +21,16 @@ void add_grid_module_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); void add_grid_module_nets_connect_duplicated_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side); + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 3b3f14203..e78981ca2 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -24,7 +24,7 @@ namespace openfpga { * 5. I/O grids in the center part of FPGA can have ports on any side *******************************************************************/ std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb) { /* We must have an regular (non-I/O) type here */ VTR_ASSERT(true == is_io_type(grid_type_descriptor)); SideManager side_manager(border_side); @@ -33,7 +33,16 @@ std::vector find_grid_module_pin_sides( return {TOP, RIGHT, BOTTOM, LEFT}; } - return std::vector(1, side_manager.get_opposite()); + if (!perimeter_cb) { + return std::vector(1, side_manager.get_opposite()); + } + /* For cbs on perimeter, exclude the border side. All the other 3 sides are ok */ + std::vector pin_sides; + pin_sides.reserve(3); + for (e_side pin_side : {TOP, RIGHT, BOTTOM, LEFT}) { + pin_sides.push_back(pin_side); + } + return pin_sides; } /******************************************************************** @@ -47,7 +56,8 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, const e_pin2pin_interc_type& pin2pin_interc_type) { + const e_side& border_side, const bool& perimeter_cb, + const e_pin2pin_interc_type& pin2pin_interc_type) { /* Find the pin side for I/O grids*/ std::vector grid_pin_sides; /* For I/O grids, we care only one side @@ -55,7 +65,7 @@ void add_grid_module_net_connect_pb_graph_pin( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index a8d5f9d12..1051ae601 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -19,7 +19,7 @@ namespace openfpga { std::vector find_grid_module_pin_sides( - t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); + t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side, const bool& perimeter_cb); void add_grid_module_net_connect_pb_graph_pin( ModuleManager& module_manager, const ModuleId& grid_module, @@ -28,7 +28,7 @@ void add_grid_module_net_connect_pb_graph_pin( const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const TileAnnotation& tile_annotation, t_pb_graph_pin* pb_graph_pin, - const e_side& border_side, + const e_side& border_side, const bool& perimeter_cb, const enum e_pin2pin_interc_type& pin2pin_interc_type); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index eaa24246b..8ffe94fda 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -42,7 +42,9 @@ static void add_grid_module_pb_type_ports( ModuleManager& module_manager, const ModuleId& grid_module, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, + const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -53,7 +55,7 @@ static void add_grid_module_pb_type_ports( */ if (true == is_io_type(grid_type_descriptor)) { grid_pin_sides = - find_grid_module_pin_sides(grid_type_descriptor, border_side); + find_grid_module_pin_sides(grid_type_descriptor, border_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -125,7 +127,8 @@ static void add_grid_module_nets_connect_pb_type_ports( const ModuleId& child_module, const size_t& child_instance, const t_sub_tile& sub_tile, const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, - const TileAnnotation& tile_annotation, const e_side& border_side) { + const TileAnnotation& tile_annotation, const e_side& border_side, + const bool& perimeter_cb) { /* Ensure that we have a valid grid_type_descriptor */ VTR_ASSERT(nullptr != grid_type_descriptor); @@ -144,7 +147,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->input_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } @@ -155,7 +158,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->output_pins[iport][ipin]), - border_side, OUTPUT2OUTPUT_INTERC); + border_side, perimeter_cb, OUTPUT2OUTPUT_INTERC); } } @@ -166,7 +169,7 @@ static void add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, child_module, child_instance, child_inst_subtile_index, vpr_device_annotation, grid_type_descriptor, tile_annotation, &(top_pb_graph_node->clock_pins[iport][ipin]), - border_side, INPUT2INPUT_INTERC); + border_side, perimeter_cb, INPUT2INPUT_INTERC); } } } @@ -1168,6 +1171,7 @@ static int build_physical_tile_module( const TileAnnotation& tile_annotation, const e_side& border_side, const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& perimeter_cb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Create a Module for the top-level physical block, and add to module manager @@ -1247,7 +1251,7 @@ static int build_physical_tile_module( /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { VTR_ASSERT(sub_tile.equivalent_sites.size() == 1); @@ -1264,7 +1268,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } else { @@ -1272,7 +1276,7 @@ static int build_physical_tile_module( /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports( module_manager, grid_module, vpr_device_annotation, phy_block_type, - tile_annotation, border_side); + tile_annotation, border_side, perimeter_cb); /* Add module nets to connect the duplicated pb_type ports to sub modules */ for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) { @@ -1290,7 +1294,7 @@ static int build_physical_tile_module( module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports( module_manager, grid_module, pb_module, child_instance, sub_tile, - vpr_device_annotation, phy_block_type, tile_annotation, border_side); + vpr_device_annotation, phy_block_type, tile_annotation, border_side, perimeter_cb); } } } @@ -1436,7 +1440,7 @@ int build_grid_modules( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, - group_config_block, verbose); + group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1446,7 +1450,7 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, device_ctx.arch->perimeter_cb, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 74797aa39..f93cd07bf 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -1175,6 +1175,7 @@ static int build_tile_port_and_nets_from_pb( const TileAnnotation& tile_annotation, const vtr::Point& pb_coord, const std::vector& pb_instances, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& ipb, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type( @@ -1201,7 +1202,7 @@ static int build_tile_port_and_nets_from_pb( * Otherwise, we will iterate all the 4 sides */ if (true == is_io_type(phy_tile)) { - grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side); + grid_pin_sides = find_grid_module_pin_sides(phy_tile, grid_side, perimeter_cb); } else { grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT}; } @@ -1378,6 +1379,7 @@ static int build_tile_module_ports_and_nets( const FabricTileId& fabric_tile_id, const std::vector& pb_instances, const std::map>& cb_instances, const std::vector& sb_instances, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1441,7 +1443,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, layer, vpr_device_annotation, rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, - fabric_tile_id, ipb, frame_view, verbose); + fabric_tile_id, ipb, perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1487,7 +1489,9 @@ static int build_tile_module( const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, - const bool& name_module_using_index, const bool& frame_view, + const bool& name_module_using_index, + const bool& perimeter_cb, + const bool& frame_view, const bool& verbose) { int status_code = CMD_EXEC_SUCCESS; @@ -1635,7 +1639,7 @@ static int build_tile_module( module_manager, tile_module, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances, cb_instances, sb_instances, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); /* Add global ports to the pb_module: * This is a much easier job after adding sub modules (instances), @@ -1709,6 +1713,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Build tile modules for the FPGA fabric"); @@ -1722,7 +1727,7 @@ int build_tile_modules(ModuleManager& module_manager, module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer, vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib, sram_model, sram_orgz_type, name_module_using_index, - frame_view, verbose); + perimeter_cb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_tile_modules.h b/openfpga/src/fabric/build_tile_modules.h index 83f219610..e3a629808 100644 --- a/openfpga/src/fabric/build_tile_modules.h +++ b/openfpga/src/fabric/build_tile_modules.h @@ -36,6 +36,7 @@ int build_tile_modules(ModuleManager& module_manager, const CircuitModelId& sram_model, const e_config_protocol_type& sram_orgz_type, const bool& name_module_using_index, + const bool& perimeter_cb, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */