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[core] fixed a bug where unique cb module is not considered as entry point

This commit is contained in:
tangxifan 2024-07-30 15:39:44 -07:00
parent 3181f2d5a3
commit a2c3af60d7
4 changed files with 14 additions and 9 deletions
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3
openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp
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@ -454,7 +454,8 @@ int build_top_module_fine_grained_child_instances(
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block, const bool& perimeter_cb,
const bool& group_config_block,
const bool& perimeter_cb,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;

3
openfpga/src/fabric/build_top_module_child_fine_grained_instance.h
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@ -44,7 +44,8 @@ int build_top_module_fine_grained_child_instances(
const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
const bool& frame_view, const bool& compact_routing_hierarchy,
const bool& duplicate_grid_pin, const FabricKey& fabric_key,
const bool& group_config_block, const bool& perimeter_cb,
const bool& group_config_block,
const bool& perimeter_cb,
const bool& verbose);
} /* end namespace openfpga */

14
openfpga/src/fabric/build_top_module_connection.cpp
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@ -1287,12 +1287,13 @@ static int build_top_module_global_net_from_clock_arch_tree(
clk_ntwk.spine_level(spine), pin, entry_dir);
/* Get the connection block module and instance at the entry point */
vtr::Point<size_t> entry_cb_coord(entry_point.x(), entry_point.y());
const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate(
entry_track_type, vtr::Point<size_t>(entry_point.x(), entry_point.y()));
ModuleId cb_module =
module_manager.find_module(generate_connection_block_module_name(
entry_track_type,
vtr::Point<size_t>(entry_point.x(), entry_point.y())));
entry_track_type, entry_cb_coord);
vtr::Point<size_t> entry_unique_cb_coord = device_rr_gsb.get_cb_unique_module(entry_track_type, entry_cb_coord).get_cb_coordinate(entry_track_type);
std::string cb_module_name = generate_connection_block_module_name(
entry_track_type, entry_unique_cb_coord);
ModuleId cb_module = module_manager.find_module(cb_module_name);
size_t cb_instance =
cb_instance_ids.at(entry_track_type)[entry_point.x()][entry_point.y()];
ModulePinInfo des_pin_info = find_connection_block_module_chan_port(
@ -1323,7 +1324,8 @@ int add_top_module_global_ports_from_grid_modules(
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) {
const RRClockSpatialLookup& rr_clock_lookup,
const bool& perimeter_cb) {
int status = CMD_EXEC_SUCCESS;
/* Add the global ports which are NOT yet added to the top-level module

3
openfpga/src/fabric/build_top_module_connection.h
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@ -42,7 +42,8 @@ int add_top_module_global_ports_from_grid_modules(
const DeviceRRGSB& device_rr_gsb,
const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb);
const RRClockSpatialLookup& rr_clock_lookup,
const bool& perimeter_cb);
void add_top_module_nets_prog_clock(ModuleManager& module_manager,
const ModuleId& top_module,