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[core] fixed a bug on inter-tile connections in top module

This commit is contained in:
tangxifan 2024-07-05 18:19:22 -07:00
parent e95b264965
commit 1f7fbfef64
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
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@ -802,13 +802,13 @@ static int build_top_module_tile_nets_between_sb_and_cb(
* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
* use is_cb_exist()
*/
if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (false == rr_gsb.is_cb_exist(cb_type)) {
continue;
}
}
if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
const RRGSB& adjacent_gsb =
device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if (false == adjacent_gsb.is_cb_exist(cb_type)) {