[core] fixed a bug where clock network size cannot impact global port on top module
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5dd0549aed
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1fd974d544
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@ -96,6 +96,12 @@ size_t TileAnnotation::global_port_default_value(
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return global_port_default_values_[global_port_id];
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}
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bool TileAnnotation::global_port_thru_dedicated_network(
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const TileGlobalPortId& global_port_id) const {
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return !global_port_clock_arch_tree_name(global_port_id).empty();
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}
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std::string TileAnnotation::global_port_clock_arch_tree_name(
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const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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@ -54,6 +54,8 @@ class TileAnnotation {
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bool global_port_is_clock(const TileGlobalPortId& global_port_id) const;
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bool global_port_is_set(const TileGlobalPortId& global_port_id) const;
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bool global_port_is_reset(const TileGlobalPortId& global_port_id) const;
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bool global_port_thru_dedicated_network(
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const TileGlobalPortId& global_port_id) const;
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std::string global_port_clock_arch_tree_name(
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const TileGlobalPortId& global_port_id) const;
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size_t global_port_default_value(
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@ -1242,11 +1242,11 @@ static int build_top_module_global_net_from_clock_arch_tree(
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if (clk_ntwk.tree_width(clk_tree) !=
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module_manager.module_port(top_module, top_module_port).get_width()) {
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VTR_LOG(
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"Clock tree '%s' does not have the same width '%lu' as the port '%'s of "
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"Clock tree '%s' does not have the same width '%lu' as the port '%s' of "
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"FPGA top module",
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clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree),
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module_manager.module_port(top_module, top_module_port)
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.get_name()
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.to_verilog_string()
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.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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@ -1323,12 +1323,19 @@ int add_top_module_global_ports_from_grid_modules(
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BasicPort global_port_to_add;
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global_port_to_add.set_name(
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tile_annotation.global_port_name(tile_global_port));
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size_t max_port_size = 0;
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for (const BasicPort& tile_port :
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tile_annotation.global_port_tile_ports(tile_global_port)) {
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max_port_size = std::max(tile_port.get_width(), max_port_size);
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/* Dedicated network has their own sizes of port */
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if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
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std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port);
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ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name);
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global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree));
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} else {
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size_t max_port_size = 0;
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for (const BasicPort& tile_port :
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tile_annotation.global_port_tile_ports(tile_global_port)) {
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max_port_size = std::max(tile_port.get_width(), max_port_size);
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}
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global_port_to_add.set_width(max_port_size);
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}
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global_port_to_add.set_width(max_port_size);
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global_ports_to_add.push_back(global_port_to_add);
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}
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}
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@ -1352,8 +1359,7 @@ int add_top_module_global_ports_from_grid_modules(
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* - If the net will be directly wired to tiles, the net will drive an input
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* of a tile
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*/
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if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port)
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.empty()) {
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if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
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status = build_top_module_global_net_from_clock_arch_tree(
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module_manager, top_module, top_module_port, rr_graph, device_rr_gsb,
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cb_instance_ids, clk_ntwk,
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