diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp
index 2ffacd1d0..c6c71c4b2 100644
--- a/libs/libarchopenfpga/src/tile_annotation.cpp
+++ b/libs/libarchopenfpga/src/tile_annotation.cpp
@@ -96,6 +96,12 @@ size_t TileAnnotation::global_port_default_value(
   return global_port_default_values_[global_port_id];
 }
 
+bool TileAnnotation::global_port_thru_dedicated_network(
+  const TileGlobalPortId& global_port_id) const {
+  return !global_port_clock_arch_tree_name(global_port_id).empty();
+}
+
+
 std::string TileAnnotation::global_port_clock_arch_tree_name(
   const TileGlobalPortId& global_port_id) const {
   VTR_ASSERT(valid_global_port_id(global_port_id));
diff --git a/libs/libarchopenfpga/src/tile_annotation.h b/libs/libarchopenfpga/src/tile_annotation.h
index 36af8a9b4..f2f3f3d75 100644
--- a/libs/libarchopenfpga/src/tile_annotation.h
+++ b/libs/libarchopenfpga/src/tile_annotation.h
@@ -54,6 +54,8 @@ class TileAnnotation {
   bool global_port_is_clock(const TileGlobalPortId& global_port_id) const;
   bool global_port_is_set(const TileGlobalPortId& global_port_id) const;
   bool global_port_is_reset(const TileGlobalPortId& global_port_id) const;
+  bool global_port_thru_dedicated_network(
+    const TileGlobalPortId& global_port_id) const;
   std::string global_port_clock_arch_tree_name(
     const TileGlobalPortId& global_port_id) const;
   size_t global_port_default_value(
diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index 84c901945..e0c86ab17 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -1242,11 +1242,11 @@ static int build_top_module_global_net_from_clock_arch_tree(
   if (clk_ntwk.tree_width(clk_tree) !=
       module_manager.module_port(top_module, top_module_port).get_width()) {
     VTR_LOG(
-      "Clock tree '%s' does not have the same width '%lu' as the port '%'s of "
+      "Clock tree '%s' does not have the same width '%lu' as the port '%s' of "
       "FPGA top module",
       clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree),
       module_manager.module_port(top_module, top_module_port)
-        .get_name()
+        .to_verilog_string()
         .c_str());
     return CMD_EXEC_FATAL_ERROR;
   }
@@ -1323,12 +1323,19 @@ int add_top_module_global_ports_from_grid_modules(
       BasicPort global_port_to_add;
       global_port_to_add.set_name(
         tile_annotation.global_port_name(tile_global_port));
-      size_t max_port_size = 0;
-      for (const BasicPort& tile_port :
-           tile_annotation.global_port_tile_ports(tile_global_port)) {
-        max_port_size = std::max(tile_port.get_width(), max_port_size);
+      /* Dedicated network has their own sizes of port */
+      if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
+        std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port);
+        ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name);
+        global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree));
+      } else {
+        size_t max_port_size = 0;
+        for (const BasicPort& tile_port :
+             tile_annotation.global_port_tile_ports(tile_global_port)) {
+          max_port_size = std::max(tile_port.get_width(), max_port_size);
+        }
+        global_port_to_add.set_width(max_port_size);
       }
-      global_port_to_add.set_width(max_port_size);
       global_ports_to_add.push_back(global_port_to_add);
     }
   }
@@ -1352,8 +1359,7 @@ int add_top_module_global_ports_from_grid_modules(
      * - If the net will be directly wired to tiles, the net will drive an input
      * of a tile
      */
-    if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port)
-           .empty()) {
+    if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) {
       status = build_top_module_global_net_from_clock_arch_tree(
         module_manager, top_module, top_module_port, rr_graph, device_rr_gsb,
         cb_instance_ids, clk_ntwk,