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[core] now netlist look ok

This commit is contained in:
tangxifan 2024-07-05 12:36:47 -07:00
parent 283aa3a1c9
commit a41f437109
2 changed files with 7 additions and 7 deletions
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6
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -753,17 +753,17 @@ static void add_top_module_nets_connect_sb_and_cb(
* is_cb_exist() FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then
* use is_cb_exist()
*/
if (TOP == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (BOTTOM == side_manager.get_side() || LEFT == side_manager.get_side()) {
if (false == rr_gsb.is_cb_exist(cb_type)) {
continue;
}
}
if (RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side()) {
if (RIGHT == side_manager.get_side() || TOP == side_manager.get_side()) {
/* Only for the condition where cbs are on perimeter, the neighbour cb will be invalid
* Bypass in such case on finding neighbour cbs
*/
if (BOTTOM == side_manager.get_side() && instance_sb_coordinate.y() == 0) {
if (TOP == side_manager.get_side() && instance_sb_coordinate.y() == device_rr_gsb.get_gsb_range().y()) {
continue;
}
if (RIGHT == side_manager.get_side() && instance_sb_coordinate.x() == device_rr_gsb.get_gsb_range().x()) {

8
openfpga/src/fabric/build_top_module_utils.cpp
View File

@ -100,13 +100,13 @@ vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(
vtr::Point<size_t> gsb_coordinate;
if ((TOP == sb_side) || (LEFT == sb_side)) {
if ((BOTTOM == sb_side) || (LEFT == sb_side)) {
gsb_coordinate.set_x(rr_gsb.get_x());
gsb_coordinate.set_y(rr_gsb.get_y());
return gsb_coordinate;
}
VTR_ASSERT((RIGHT == sb_side) || (BOTTOM == sb_side));
VTR_ASSERT((RIGHT == sb_side) || (TOP == sb_side));
/* RIGHT side: x + 1 */
if (RIGHT == sb_side) {
@ -115,9 +115,9 @@ vtr::Point<size_t> find_top_module_gsb_coordinate_by_sb_side(
}
/* BOTTOM side: y - 1 */
if (BOTTOM == sb_side) {
if (TOP == sb_side) {
gsb_coordinate.set_x(rr_gsb.get_x());
gsb_coordinate.set_y(rr_gsb.get_y() - 1);
gsb_coordinate.set_y(rr_gsb.get_y() + 1);
}
return gsb_coordinate;