dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
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Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
08bd6d00d3
[core] code format
2024-04-11 15:04:08 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
5960cc14aa
[core] fixed a bug
2024-04-11 13:04:47 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
435e83c530
[core] add port side to tile ports
2024-04-10 17:38:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
d156de060e
[core] adding pin side attribute to module manager
2024-04-10 16:19:28 -07:00
b0be9fe75d
[core] developing xml writer for fabric pin phy loc
2024-04-10 15:51:26 -07:00
47baaff94c
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
2024-04-10 13:30:02 -07:00
3d4f1505b6
[core] code format
2023-10-20 22:02:56 -07:00
66c3226fad
[core] now follow module unique index when naming grouped configuration memories
2023-10-20 22:01:19 -07:00
e4b204f2e4
[core] code format
2023-10-20 21:14:07 -07:00
76a4b8a82b
[core] remove the prefix of grouped memory blocks
2023-10-20 21:13:37 -07:00
c4bce834e4
[core] code format
2023-09-25 22:34:39 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
1624dc9764
[core] code format
2023-09-25 21:13:50 -07:00
76f446caec
[core] fixed a bug
2023-09-25 21:13:11 -07:00
dbd466cdec
[core] now support tile port merge
2023-09-25 18:16:24 -07:00
3adf81046a
[core] code format
2023-09-25 17:22:26 -07:00
5e269e8bc4
[core] support port merging at grid modules
2023-09-25 17:21:58 -07:00
edb0e687f1
[core] code format
2023-09-23 12:15:53 -07:00
11de8965a8
[core] fixed some bugs
2023-09-23 12:15:31 -07:00
860cfd53c6
[core] fixed critical bugs in renaming modules
2023-09-23 11:51:31 -07:00
ca3617a029
[core] code format
2023-09-20 20:37:27 -07:00
1ef38b6a64
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
2023-09-20 20:34:21 -07:00
c105b56bf0
[core] code format
2023-09-18 23:31:27 -07:00
43fd08a3fe
[core] fixed a bug
2023-09-18 23:31:09 -07:00
1daabb990e
[core] code format
2023-09-18 15:35:13 -07:00
110301a2e4
[core] now tile port naming can follow index
2023-09-18 15:34:40 -07:00
ef97127c63
[core] fixed some bugs in testbenches when renaming top modules
2023-09-17 22:34:00 -07:00
d5152dc16d
[core] fixed a bug on the hierarchy writer
2023-09-17 17:42:25 -07:00
37573abc22
[core] code format
2023-09-15 23:32:40 -07:00
c85c64eb5a
[core] syntax
2023-09-15 23:30:34 -07:00
bc407e5d69
[core] code complete for rename modules
2023-09-15 23:22:31 -07:00
2a45b49890
[core] developing renaming commands. options and functions
2023-09-15 19:15:18 -07:00
717906ea17
[core] code format
2023-08-25 15:13:39 -07:00
89b392a51f
[core] adapt changes in is_sb_exist()
2023-08-25 15:13:00 -07:00
66cc375996
[core] remove debugging messages
2023-08-18 22:08:47 -07:00
19d4d9a16d
[core] code format
2023-08-18 21:05:26 -07:00
fc523bed32
[core] fixed some bugs in spotting the correct pin index of given subtiles
2023-08-18 21:04:37 -07:00
3d8f76269a
[core] fixed a bug when io is in the center of 3x3 fabric
2023-08-18 12:42:15 -07:00
e9fd22790d
[core] fixed a bug where pass thru cb blocks are not connected in tiles
2023-08-17 15:26:32 -07:00
94d80a9b7c
[core] code format
2023-08-08 16:28:56 -07:00
867da98d3f
[core] update to use latest api from vpr upstream
2023-08-08 16:28:19 -07:00
4d37421735
[core] fixed a bug on loading subkey to support fabric keys
2023-08-07 10:40:22 -07:00
18acb39fad
[core] fixed a bug where heterogeneous fabric may fail
2023-08-06 22:12:32 -07:00
a1f8b3c441
[core] fixed a bug on bitstream generator on supporting group_config_block
2023-08-05 21:58:03 -07:00
68f07d6fc9
[core] code format
2023-08-05 20:53:58 -07:00
f4d7ad2bd1
[core] trying to fix the bug on instance naming so that bitstream generation can work
2023-08-05 13:38:51 -07:00
9a23dc7bff
[core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block
2023-08-04 21:20:21 -07:00
7d8d686f74
[core] add status codes to build grid modules
2023-08-04 16:52:43 -07:00
bb9cf6dbcb
[core] fixed a critical bug which causes undriven nets on config bus in group config block
2023-08-04 16:45:15 -07:00
64c0839e30
[core] now verilog writer supports memory group modules
2023-08-04 16:11:33 -07:00
a0f81a5bf2
[core] now verilog generator can output feedthrough memory module to files
2023-08-04 13:34:38 -07:00
5bc8925c3a
[core] fixed multiple bugs on fabric generator on supporting group_config_block
2023-08-04 12:36:59 -07:00
3c2518ac70
[core] adding debugging message when verbose is enabled
2023-08-04 11:20:05 -07:00
99bda2e5b0
[core] debugging
2023-08-03 22:50:14 -07:00
2aeeb0cacf
[core] fixed a bug which causes reg tests failed
2023-08-03 22:13:27 -07:00
d3895c3dc0
[core] code format
2023-08-03 17:34:25 -07:00
f4cbc95053
[core] syntax
2023-08-03 17:33:57 -07:00
5618f1d567
[core] now bitgen uses config child types
2023-08-03 16:06:19 -07:00
3331540ed6
[core] using config child type in bitstream generation
2023-08-03 14:24:22 -07:00
2facde2097
[core] reworked fabric generator to use config child type
2023-08-03 12:57:50 -07:00
5895a1d96b
[core] reworking fabric generator based on latest changes on configurable children
2023-08-02 22:50:19 -07:00
27cae41123
[core] rework physical and logical types of configurable child
2023-08-02 20:37:27 -07:00
87f2822ef8
[core] working on logical and physical children
2023-08-02 19:46:27 -07:00
c05f12ac11
[core] sync up logical-to-physical configurable child mapping after physical memory build-up
2023-08-02 12:24:16 -07:00
470ab84489
[core] developing group config block support for routing module
2023-08-01 22:57:22 -07:00
53050b94ab
[core] developing memory group modules in grid modules
2023-08-01 17:50:03 -07:00
23643f3fb1
[core] developing the physical memory block builder
2023-07-31 22:57:26 -07:00
2d2b8f67aa
[core] adding new option '--group_config_block' to command 'build_fabric'
2023-07-31 17:32:48 -07:00
beaa687a20
[core] fixed bugs on supporting heterogeneous blocks in tile modules
2023-07-27 20:29:18 -07:00
156cb800aa
[core] fixed a critical bug which causes wrong connections in tile modules
2023-07-27 12:22:16 -07:00
dd486f5ccb
[core] fixed a bug on checking if cb is in a tile
2023-07-27 11:14:05 -07:00
cfec6c88f1
[core] fixed a bug in cb instance naming
2023-07-27 10:59:46 -07:00
be0715a81c
[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules
2023-07-27 10:42:56 -07:00
97219fd825
[core] add more verbose to help debug failed test cases
2023-07-26 23:26:11 -07:00
83428a209e
[core] fixed a bug on io indexing which causes tile-based test cases failed in dv
2023-07-25 16:03:50 -07:00
6ecbbb3a94
[core] fixed a bug in fabric bitgen due to tile modules
2023-07-25 14:49:12 -07:00
64698443c9
[core] fixed a bug on io location map for tile modules
2023-07-24 22:11:57 -07:00
2105abdbca
[core] fixed a bug
2023-07-24 21:26:29 -07:00
e7d714b94d
[core] fixed a bug on the tile module port addition: some grid output was not pulled out
2023-07-24 21:21:25 -07:00
b8d080b08e
[core] fixed a bug where undriven cb ports are not connected to tile
2023-07-24 20:40:25 -07:00
3745897ff6
[core] fixed a few bugs
2023-07-24 16:10:29 -07:00
48b0ba8b78
[core] format
2023-07-24 15:00:26 -07:00
4294914987
[core] fixed compiler warnings
2023-07-24 14:59:43 -07:00
812473ef04
[core] fixed the bug on io location map for tiled top module
2023-07-24 14:50:39 -07:00
da36b735c6
[core] syntax
2023-07-24 12:13:45 -07:00
f031148959
[core] syntax
2023-07-23 22:39:36 -07:00
f551188d0f
[core] developed tile directs to support tile modules
2023-07-23 21:45:45 -07:00
14666f3ae5
[core] sync
2023-07-23 20:45:59 -07:00
0b3b7b5472
[core] hotfix
2023-07-23 13:39:06 -07:00
1ee7448070
[core] supporting tile annotation (for global port) in tile modules
2023-07-23 13:38:16 -07:00
399259ea1d
[core] adding prog clock arch support for tile modules
2023-07-23 13:11:13 -07:00
0f3f4b0d81
[core] now tile module use unique port name (for heterogeneous blocks)
2023-07-22 23:55:54 -07:00
003d9515ff
[core] developing tile-based top module builder
2023-07-22 17:13:30 -07:00
chungshien
tangxifan